[people/ms/u-boot.git] / include / configs / alt.h

/*
 * include/configs/alt.h
 *     This file is alt board configuration.
 *
 * Copyright (C) 2014 Renesas Electronics Corporation
 *
 * SPDX-License-Identifier: GPL-2.0
 */

#ifndef __ALT_H
#define __ALT_H

#undef DEBUG
#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"

#include "rcar-gen2-common.h"

#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
#define CONFIG_SYS_INIT_SP_ADDR		0x7003FFFC
#else
#define CONFIG_SYS_INIT_SP_ADDR		0xE633FFFC
#endif
#define STACK_AREA_SIZE			0xC000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* SCIF */

/* FLASH */
#define CONFIG_SPI
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK        20000000u
#define CONFIG_SYS_CLK_FREQ     RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ  (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
#define CONFIG_PLL1_CLK_FREQ    (CONFIG_SYS_CLK_FREQ * 156 / 2)
#define CONFIG_P_CLK_FREQ	(CONFIG_PLL1_CLK_FREQ / 24)

#define CONFIG_SYS_TMU_CLK_DIV  4

/* i2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SH
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS       3
#define CONFIG_SYS_I2C_SH_SPEED0	400000
#define CONFIG_SYS_I2C_SH_SPEED1	400000
#define CONFIG_SYS_I2C_SH_SPEED2	400000
#define CONFIG_SH_I2C_DATA_HIGH		4
#define CONFIG_SH_I2C_DATA_LOW		5
#define CONFIG_SH_I2C_CLOCK		10000000

#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */

/* USB */
#define CONFIG_USB_EHCI_RMOBILE
#define CONFIG_USB_MAX_CONTROLLER_COUNT	2

/* MMCIF */
#define CONFIG_SH_MMCIF
#define CONFIG_SH_MMCIF_ADDR		0xee200000
#define CONFIG_SH_MMCIF_CLK		48000000

/* Module stop status bits */
/* INTC-RT */
#define CONFIG_SMSTP0_ENA	0x00400000
/* MSIF */
#define CONFIG_SMSTP2_ENA	0x00002000
/* INTC-SYS, IRQC */
#define CONFIG_SMSTP4_ENA	0x00000180
/* SCIF2 */
#define CONFIG_SMSTP7_ENA	0x00080000

/* SDHI */
#define CONFIG_SH_SDHI_FREQ		97500000

#endif /* __ALT_H */
Commit	Line	Data
cff2f5f0 NI	1	/*
	2	* include/configs/alt.h
	3	* This file is alt board configuration.
	4	*
	5	* Copyright (C) 2014 Renesas Electronics Corporation
	6	*
	7	* SPDX-License-Identifier: GPL-2.0
	8	*/
	9
	10	#ifndef __ALT_H
	11	#define __ALT_H
	12
	13	#undef DEBUG
1cc95f6e	14	#define CONFIG_ARCH_RMOBILE_BOARD_STRING "Alt"
cff2f5f0	15
5ca6dfe6	16	#include "rcar-gen2-common.h"
cff2f5f0	17
1cc95f6e	18	#if defined(CONFIG_ARCH_RMOBILE_EXTRAM_BOOT)
c9b59bf7 NI	19	#define CONFIG_SYS_INIT_SP_ADDR 0x7003FFFC
c9b59bf7 NI	20	#else
cff2f5f0	21	#define CONFIG_SYS_INIT_SP_ADDR 0xE633FFFC
c9b59bf7	22	#endif
cff2f5f0 NI	23	#define STACK_AREA_SIZE 0xC000
	24	#define LOW_LEVEL_MERAM_STACK \
	25	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	26
	27	/* MEMORY */
5ca6dfe6 NI	28	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	29	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	30	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
cff2f5f0 NI	31
cff2f5f0 NI	32	/* SCIF */
cff2f5f0 NI	33
	34	/* FLASH */
	35	#define CONFIG_SPI
cff2f5f0	36	#define CONFIG_SPI_FLASH_QUAD
cff2f5f0	37
cff2f5f0	38	/* SH Ether */
cff2f5f0 NI	39	#define CONFIG_SH_ETHER_USE_PORT 0
	40	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	41	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	42	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	43	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	44	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
cff2f5f0 NI	45	#define CONFIG_BITBANGMII
	46	#define CONFIG_BITBANGMII_MULTI
	47
	48	/* Board Clock */
	49	#define RMOBILE_XTAL_CLK 20000000u
	50	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
	51	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) /* EXT / 2 */
	52	#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 156 / 2)
	53	#define CONFIG_P_CLK_FREQ (CONFIG_PLL1_CLK_FREQ / 24)
cff2f5f0 NI	54
	55	#define CONFIG_SYS_TMU_CLK_DIV 4
	56
	57	/* i2c */
cff2f5f0 NI	58	#define CONFIG_SYS_I2C
	59	#define CONFIG_SYS_I2C_SH
	60	#define CONFIG_SYS_I2C_SLAVE 0x7F
	61	#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 3
cff2f5f0	62	#define CONFIG_SYS_I2C_SH_SPEED0 400000
cff2f5f0	63	#define CONFIG_SYS_I2C_SH_SPEED1 400000
cff2f5f0 NI	64	#define CONFIG_SYS_I2C_SH_SPEED2 400000
	65	#define CONFIG_SH_I2C_DATA_HIGH 4
	66	#define CONFIG_SH_I2C_DATA_LOW 5
	67	#define CONFIG_SH_I2C_CLOCK 10000000
	68
	69	#define CONFIG_SYS_I2C_POWERIC_ADDR 0x58 /* da9063 */
	70
7ffc8dfb	71	/* USB */
7ffc8dfb NI	72	#define CONFIG_USB_EHCI_RMOBILE
	73	#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
	74
2b8c0814	75	/* MMCIF */
2b8c0814 NI	76	#define CONFIG_SH_MMCIF
	77	#define CONFIG_SH_MMCIF_ADDR 0xee200000
	78	#define CONFIG_SH_MMCIF_CLK 48000000
	79
8e2e5886 NI	80	/* Module stop status bits */
	81	/* INTC-RT */
	82	#define CONFIG_SMSTP0_ENA 0x00400000
	83	/* MSIF */
	84	#define CONFIG_SMSTP2_ENA 0x00002000
	85	/* INTC-SYS, IRQC */
	86	#define CONFIG_SMSTP4_ENA 0x00000180
	87	/* SCIF2 */
	88	#define CONFIG_SMSTP7_ENA 0x00080000
	89
25f9613f NI	90	/* SDHI */
	91	#define CONFIG_SH_SDHI_FREQ 97500000
	92
cff2f5f0	93	#endif /* __ALT_H */