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ed01e45c VH |
1 | /* |
2 | * am3517_evm.h - Default configuration for AM3517 EVM board. | |
3 | * | |
4 | * Author: Vaibhav Hiremath <hvaibhav@ti.com> | |
5 | * | |
6 | * Based on omap3_evm_config.h | |
7 | * | |
8 | * Copyright (C) 2010 Texas Instruments Incorporated | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
ed01e45c VH |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
3f53e619 DW |
16 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ |
17 | ||
1a5038ca | 18 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
ed01e45c | 19 | |
3f53e619 DW |
20 | /* |
21 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
22 | * 64 bytes before this address should be set aside for u-boot.img's | |
23 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
24 | * other needs. | |
25 | */ | |
26 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
27 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
28 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
29 | ||
ed01e45c | 30 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
987ec585 | 31 | #include <asm/arch/omap.h> |
ed01e45c | 32 | |
3f53e619 DW |
33 | #define CONFIG_MISC_INIT_R |
34 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ | |
35 | #define CONFIG_SETUP_MEMORY_TAGS | |
36 | #define CONFIG_INITRD_TAG | |
37 | #define CONFIG_REVISION_TAG | |
ed01e45c VH |
38 | |
39 | /* Clock Defines */ | |
40 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
41 | #define V_SCLK (V_OSCK >> 1) | |
42 | ||
3f53e619 DW |
43 | /* Size of malloc() pool */ |
44 | #define CONFIG_SYS_MALLOC_LEN (16 << 20) | |
ed01e45c | 45 | |
3f53e619 | 46 | /* Hardware drivers */ |
ed01e45c | 47 | |
3f53e619 | 48 | /* NS16550 Configuration */ |
ed01e45c | 49 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ |
ed01e45c VH |
50 | #define CONFIG_SYS_NS16550_SERIAL |
51 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
52 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
53 | ||
3f53e619 | 54 | /* select serial console configuration */ |
ed01e45c VH |
55 | #define CONFIG_CONS_INDEX 3 |
56 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
57 | #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ | |
58 | ||
59 | /* allow to overwrite serial and ethaddr */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
ed01e45c VH |
61 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ |
62 | 115200} | |
3f53e619 | 63 | |
7dc27b05 AKG |
64 | /* |
65 | * USB configuration | |
95de1e2f PK |
66 | * Enable CONFIG_USB_MUSB_HOST for Host functionalities MSC, keyboard |
67 | * Enable CONFIG_USB_MUSB_GADGET for Device functionalities. | |
7dc27b05 | 68 | */ |
88919ff7 | 69 | #define CONFIG_USB_MUSB_AM35X |
95de1e2f | 70 | #define CONFIG_USB_MUSB_PIO_ONLY |
7dc27b05 | 71 | |
88919ff7 | 72 | #ifdef CONFIG_USB_MUSB_AM35X |
7dc27b05 | 73 | |
95de1e2f | 74 | #ifdef CONFIG_USB_MUSB_HOST |
7dc27b05 | 75 | |
7dc27b05 AKG |
76 | #ifdef CONFIG_USB_KEYBOARD |
77 | #define CONFIG_SYS_USB_EVENT_POLL | |
78 | #define CONFIG_PREBOOT "usb start" | |
79 | #endif /* CONFIG_USB_KEYBOARD */ | |
80 | ||
95de1e2f | 81 | #endif /* CONFIG_USB_MUSB_HOST */ |
88919ff7 | 82 | |
95de1e2f | 83 | #ifdef CONFIG_USB_MUSB_GADGET |
88919ff7 IY |
84 | #define CONFIG_USB_ETHER |
85 | #define CONFIG_USB_ETH_RNDIS | |
95de1e2f | 86 | #endif /* CONFIG_USB_MUSB_GADGET */ |
88919ff7 IY |
87 | |
88 | #endif /* CONFIG_USB_MUSB_AM35X */ | |
7dc27b05 | 89 | |
3f53e619 | 90 | /* I2C */ |
6789e84e HS |
91 | #define CONFIG_SYS_I2C |
92 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
93 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
ed01e45c | 94 | |
3f53e619 | 95 | /* Ethernet */ |
18a02e80 TR |
96 | #define CONFIG_DRIVER_TI_EMAC |
97 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
98 | #define CONFIG_MII | |
99 | #define CONFIG_BOOTP_DEFAULT | |
100 | #define CONFIG_BOOTP_DNS | |
101 | #define CONFIG_BOOTP_DNS2 | |
102 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
103 | #define CONFIG_NET_RETRY_COUNT 10 | |
104 | ||
3f53e619 DW |
105 | /* Board NAND Info. */ |
106 | #ifdef CONFIG_NAND | |
107 | #define CONFIG_NAND_OMAP_GPMC | |
108 | #define CONFIG_NAND_OMAP_GPMC_PREFETCH | |
109 | #define CONFIG_BCH | |
ed01e45c VH |
110 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
111 | /* to access nand */ | |
112 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
113 | /* to access */ | |
114 | /* nand at CS0 */ | |
ed01e45c VH |
115 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ |
116 | /* NAND devices */ | |
3f53e619 DW |
117 | #define CONFIG_SYS_NAND_BUSWIDTH_16BIT |
118 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
119 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
120 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
121 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
122 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
123 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
124 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, 10, \ | |
125 | 11, 12, 13, 14, 16, 17, 18, 19, 20, \ | |
126 | 21, 22, 23, 24, 25, 26, 27, 28, 30, \ | |
127 | 31, 32, 33, 34, 35, 36, 37, 38, 39, \ | |
128 | 40, 41, 42, 44, 45, 46, 47, 48, 49, \ | |
129 | 50, 51, 52, 53, 54, 55, 56 } | |
130 | ||
131 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
132 | #define CONFIG_SYS_NAND_ECCBYTES 13 | |
133 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW | |
134 | #define CONFIG_SYS_NAND_MAX_OOBFREE 2 | |
135 | #define CONFIG_SYS_NAND_MAX_ECCPOS 56 | |
136 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
137 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
138 | #define CONFIG_MTD_PARTITIONS /* required for UBI partition support */ | |
139 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
140 | /* NAND block size is 128 KiB. Synchronize these values with | |
141 | * corresponding Device Tree entries in Linux: | |
142 | * MLO(SPL) 4 * NAND_BLOCK_SIZE = 512 KiB @ 0x000000 | |
143 | * U-Boot 15 * NAND_BLOCK_SIZE = 1920 KiB @ 0x080000 | |
144 | * U-Boot environment 2 * NAND_BLOCK_SIZE = 256 KiB @ 0x260000 | |
145 | * Kernel 64 * NAND_BLOCK_SIZE = 8 MiB @ 0x2A0000 | |
146 | * DTB 4 * NAND_BLOCK_SIZE = 512 KiB @ 0xAA0000 | |
147 | * RootFS Remaining Flash Space @ 0xB20000 | |
148 | */ | |
149 | #define MTDIDS_DEFAULT "nand0=omap2-nand.0" | |
150 | #define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ | |
151 | "512k(MLO)," \ | |
152 | "1920k(u-boot)," \ | |
153 | "256k(u-boot-env)," \ | |
154 | "8m(kernel)," \ | |
155 | "512k(dtb)," \ | |
156 | "-(rootfs)" | |
157 | #else | |
158 | #define MTDIDS_DEFAULT | |
159 | #define MTDPARTS_DEFAULT | |
160 | #endif /* CONFIG_NAND */ | |
ed01e45c VH |
161 | |
162 | /* Environment information */ | |
ed01e45c | 163 | |
b3f44c21 | 164 | #define CONFIG_BOOTFILE "uImage" |
ed01e45c VH |
165 | |
166 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
167 | "loadaddr=0x82000000\0" \ | |
49473ada | 168 | "console=ttyO2,115200n8\0" \ |
45776e36 DW |
169 | "fdtfile=am3517-evm.dtb\0" \ |
170 | "fdtaddr=0x82C00000\0" \ | |
171 | "vram=16M\0" \ | |
172 | "bootenv=uEnv.txt\0" \ | |
173 | "cmdline=\0" \ | |
174 | "optargs=\0" \ | |
3f53e619 DW |
175 | "mtdids=" MTDIDS_DEFAULT "\0" \ |
176 | "mtdparts=" MTDPARTS_DEFAULT "\0" \ | |
122e6e0a | 177 | "mmcdev=0\0" \ |
45776e36 DW |
178 | "mmcpart=1\0" \ |
179 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
180 | "mmcrootfstype=ext4 rootwait fixrtc\0" \ | |
ed01e45c | 181 | "mmcargs=setenv bootargs console=${console} " \ |
3f53e619 | 182 | "${mtdparts} " \ |
45776e36 DW |
183 | "${optargs} " \ |
184 | "root=${mmcroot} " \ | |
185 | "rootfstype=${mmcrootfstype} " \ | |
186 | "${cmdline}\0" \ | |
ed01e45c | 187 | "nandargs=setenv bootargs console=${console} " \ |
3f53e619 DW |
188 | "${mtdparts} " \ |
189 | "${optargs} " \ | |
190 | "root=ubi0:rootfs rw ubi.mtd=rootfs " \ | |
191 | "rootfstype=ubifs rootwait " \ | |
192 | "${cmdline}\0" \ | |
45776e36 DW |
193 | "loadbootenv=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootenv}\0"\ |
194 | "importbootenv=echo Importing environment from mmc ...; " \ | |
195 | "env import -t ${loadaddr} ${filesize}\0" \ | |
ed01e45c VH |
196 | "bootscript=echo Running bootscript from mmc ...; " \ |
197 | "source ${loadaddr}\0" \ | |
45776e36 DW |
198 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${bootfile}\0" \ |
199 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdtaddr} ${fdtfile}\0" \ | |
ed01e45c VH |
200 | "mmcboot=echo Booting from mmc ...; " \ |
201 | "run mmcargs; " \ | |
45776e36 | 202 | "bootz ${loadaddr} - ${fdtaddr}\0" \ |
ed01e45c VH |
203 | "nandboot=echo Booting from nand ...; " \ |
204 | "run nandargs; " \ | |
3f53e619 DW |
205 | "nand read ${loadaddr} 2a0000 800000; " \ |
206 | "nand read ${fdtaddr} aa0000 80000; " \ | |
207 | "bootm ${loadaddr} - ${fdtaddr}\0" \ | |
ed01e45c VH |
208 | |
209 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 210 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
45776e36 DW |
211 | "echo SD/MMC found on device $mmcdev; " \ |
212 | "if run loadbootenv; then " \ | |
213 | "run importbootenv; " \ | |
214 | "fi; " \ | |
215 | "echo Checking if uenvcmd is set ...; " \ | |
216 | "if test -n $uenvcmd; then " \ | |
217 | "echo Running uenvcmd ...; " \ | |
218 | "run uenvcmd; " \ | |
219 | "fi; " \ | |
220 | "echo Running default loadimage ...; " \ | |
221 | "setenv bootfile zImage; " \ | |
222 | "if run loadimage; then " \ | |
223 | "run loadfdt; " \ | |
224 | "run mmcboot; " \ | |
ed01e45c VH |
225 | "fi; " \ |
226 | "else run nandboot; fi" | |
227 | ||
3f53e619 DW |
228 | /* Miscellaneous configurable options */ |
229 | #define CONFIG_AUTO_COMPLETE | |
230 | #define CONFIG_CMDLINE_EDITING | |
3f53e619 | 231 | #define CONFIG_SYS_LONGHELP |
3f53e619 DW |
232 | |
233 | /* We set the max number of command args high to avoid HUSH bugs. */ | |
234 | #define CONFIG_SYS_MAXARGS 64 | |
235 | ||
236 | /* Console I/O Buffer Size */ | |
237 | #define CONFIG_SYS_CBSIZE 512 | |
ed01e45c | 238 | /* Print Buffer Size */ |
3f53e619 DW |
239 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
240 | + sizeof(CONFIG_SYS_PROMPT) + 16) | |
ed01e45c | 241 | /* Boot Argument Buffer Size */ |
3f53e619 DW |
242 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
243 | ||
ed01e45c VH |
244 | /* memtest works on */ |
245 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
246 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
247 | 0x01F00000) /* 31MB */ | |
248 | ||
249 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
250 | /* address */ | |
251 | ||
252 | /* | |
253 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
254 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
255 | * This rate is divided by a local divisor. | |
256 | */ | |
257 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
258 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
ed01e45c | 259 | |
3f53e619 DW |
260 | /* Physical Memory Map */ |
261 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
262 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
263 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) | |
264 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
265 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
266 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
267 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
268 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
269 | GENERATED_GBL_DATA_SIZE) | |
ed01e45c | 270 | |
3f53e619 | 271 | /* FLASH and environment organization */ |
ed01e45c VH |
272 | |
273 | /* **** PISMO SUPPORT *** */ | |
ed01e45c VH |
274 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ |
275 | /* on one chip */ | |
276 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
277 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
278 | ||
3f53e619 | 279 | #if defined(CONFIG_NAND) |
222a3113 | 280 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
6cbec7b3 | 281 | #endif |
ed01e45c VH |
282 | |
283 | /* Monitor at start of flash */ | |
284 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
285 | ||
6cbec7b3 | 286 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
3f53e619 DW |
287 | #define CONFIG_ENV_SIZE CONFIG_SYS_ENV_SECT_SIZE |
288 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
6cbec7b3 LC |
289 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET |
290 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
5059a2a4 TR |
291 | |
292 | /* Defines for SPL */ | |
47f7bcae | 293 | #define CONFIG_SPL_FRAMEWORK |
5059a2a4 | 294 | #define CONFIG_SPL_NAND_SIMPLE |
138daa7b | 295 | #define CONFIG_SPL_TEXT_BASE 0x40200000 |
fa2f81b0 TR |
296 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
297 | CONFIG_SPL_TEXT_BASE) | |
5059a2a4 TR |
298 | |
299 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
300 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
301 | ||
e2ccdf89 | 302 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
3f53e619 | 303 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
5059a2a4 | 304 | |
6f2f01b9 SW |
305 | #define CONFIG_SPL_NAND_BASE |
306 | #define CONFIG_SPL_NAND_DRIVERS | |
307 | #define CONFIG_SPL_NAND_ECC | |
5059a2a4 | 308 | |
ed01e45c | 309 | #endif /* __CONFIG_H */ |