[people/ms/u-boot.git] / include / configs / am3517_evm.h

/*
 * am3517_evm.h - Default configuration for AM3517 EVM board.
 *
 * Author: Vaibhav Hiremath <hvaibhav@ti.com>
 *
 * Based on omap3_evm_config.h
 *
 * Copyright (C) 2010 Texas Instruments Incorporated
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_OMAP		1	/* in a TI OMAP core */
#define CONFIG_OMAP34XX		1	/* which is a 34XX */
#define CONFIG_OMAP3_AM3517EVM	1	/* working with AM3517EVM */

#define CONFIG_EMIF4	/* The chip has EMIF4 controller */

#include <asm/arch/cpu.h>		/* get chip and board defs */
#include <asm/arch/omap3.h>

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO		1
#define CONFIG_DISPLAY_BOARDINFO	1

/* Clock Defines */
#define V_OSCK			26000000	/* Clock output from T2 */
#define V_SCLK			(V_OSCK >> 1)

#define CONFIG_MISC_INIT_R

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs */
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1
#define CONFIG_REVISION_TAG		1

/*
 * Size of malloc() pool
 */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB sector */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (128 << 10))
/*
 * DDR related
 */
#define CONFIG_SYS_CS0_SIZE		(256 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			48000000	/* 48MHz (APLL96/2) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX		3
#define CONFIG_SYS_NS16550_COM3		OMAP34XX_UART3
#define CONFIG_SERIAL3			3	/* UART3 on AM3517 EVM */

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}
#define CONFIG_MMC			1
#define CONFIG_GENERIC_MMC		1
#define CONFIG_OMAP_HSMMC		1
#define CONFIG_DOS_PARTITION		1

/*
 * USB configuration
 * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard
 * Enable CONFIG_MUSB_GADGET for Device functionalities.
 */
#define CONFIG_USB_MUSB_AM35X
#define CONFIG_MUSB_HOST
#define CONFIG_MUSB_PIO_ONLY

#ifdef CONFIG_USB_MUSB_AM35X

#ifdef CONFIG_MUSB_HOST
#define CONFIG_CMD_USB

#define CONFIG_USB_STORAGE
#define CONGIG_CMD_STORAGE
#define CONFIG_CMD_FAT

#ifdef CONFIG_USB_KEYBOARD
#define CONFIG_SYS_USB_EVENT_POLL
#define CONFIG_PREBOOT "usb start"
#endif /* CONFIG_USB_KEYBOARD */

#endif /* CONFIG_MUSB_HOST */

#ifdef CONFIG_MUSB_GADGET
#define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#endif /* CONFIG_MUSB_GADGET */

#endif /* CONFIG_USB_MUSB_AM35X */

/* commands to include */
#include <config_cmd_default.h>

#define CONFIG_CMD_EXT2		/* EXT2 Support			*/
#define CONFIG_CMD_FAT		/* FAT support			*/
#define CONFIG_CMD_JFFS2	/* JFFS2 Support		*/

#define CONFIG_CMD_I2C		/* I2C serial bus support	*/
#define CONFIG_CMD_MMC		/* MMC support			*/
#define CONFIG_CMD_NAND		/* NAND support			*/
#define CONFIG_CMD_DHCP
#undef CONFIG_CMD_PING

#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect	*/
#undef CONFIG_CMD_FPGA		/* FPGA configuration Support	*/
#undef CONFIG_CMD_IMI		/* iminfo			*/
#undef CONFIG_CMD_IMLS		/* List all found images	*/

#define CONFIG_SYS_NO_FLASH
#define CONFIG_HARD_I2C			1
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		1
#define CONFIG_DRIVER_OMAP34XX_I2C	1

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
/*
 * Board NAND Info.
 */
#define CONFIG_SYS_NAND_ADDR		NAND_BASE	/* physical address */
							/* to access nand */
#define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */
							/* to access */
							/* nand at CS0 */

#define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of */
							/* NAND devices */
#define CONFIG_JFFS2_NAND
/* nand device jffs2 lives on */
#define CONFIG_JFFS2_DEV		"nand0"
/* start of jffs2 partition */
#define CONFIG_JFFS2_PART_OFFSET	0x680000
#define CONFIG_JFFS2_PART_SIZE		0xf980000	/* sz of jffs2 part */

/* Environment information */
#define CONFIG_BOOTDELAY	10

#define CONFIG_BOOTFILE		"uImage"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"loadaddr=0x82000000\0" \
	"console=ttyO2,115200n8\0" \
	"mmcdev=0\0" \
	"mmcargs=setenv bootargs console=${console} " \
		"root=/dev/mmcblk0p2 rw rootwait\0" \
	"nandargs=setenv bootargs console=${console} " \
		"root=/dev/mtdblock4 rw " \
		"rootfstype=jffs2\0" \
	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
	"bootscript=echo Running bootscript from mmc ...; " \
		"source ${loadaddr}\0" \
	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"run mmcargs; " \
		"bootm ${loadaddr}\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${loadaddr} 280000 400000; " \
		"bootm ${loadaddr}\0" \

#define CONFIG_BOOTCOMMAND \
	"mmc dev ${mmcdev}; if mmc rescan; then " \
		"if run loadbootscript; then " \
			"run bootscript; " \
		"else " \
			"if run loaduimage; then " \
				"run mmcboot; " \
			"else run nandboot; " \
			"fi; " \
		"fi; " \
	"else run nandboot; fi"

#define CONFIG_AUTO_COMPLETE	1
/*
 * Miscellaneous configurable options
 */
#define V_PROMPT			"AM3517_EVM # "

#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		V_PROMPT
#define CONFIG_SYS_CBSIZE		512	/* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		32	/* max number of command */
						/* args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	(OMAP34XX_SDRC_CS0)
#define CONFIG_SYS_MEMTEST_END		(OMAP34XX_SDRC_CS0 + \
					0x01F00000) /* 31MB */

#define CONFIG_SYS_LOAD_ADDR		(OMAP34XX_SDRC_CS0) /* default load */
								/* address */

/*
 * AM3517 has 12 GP timers, they can be driven by the system clock
 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
 * This rate is divided by a local divisor.
 */
#define CONFIG_SYS_TIMERBASE		OMAP34XX_GPT2
#define CONFIG_SYS_PTV			2	/* Divisor: 2^(PTV+1) => 8 */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	2	/* CS1 may or may not be populated */
#define PHYS_SDRAM_1		OMAP34XX_SDRC_CS0
#define PHYS_SDRAM_2		OMAP34XX_SDRC_CS1

/*-----------------------------------------------------------------------
 * FLASH and environment organization
 */

/* **** PISMO SUPPORT *** */

/* Configure the PISMO */
#define PISMO1_NAND_SIZE		GPMC_SIZE_128M
#define PISMO1_ONEN_SIZE		GPMC_SIZE_128M

#define CONFIG_SYS_MAX_FLASH_SECT	520	/* max number of sectors */
						/* on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of flash banks */
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#if defined(CONFIG_CMD_NAND)
#define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE
#endif

/* Monitor at start of flash */
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE

#define CONFIG_NAND_OMAP_GPMC
#define GPMC_NAND_ECC_LP_x16_LAYOUT	1
#define CONFIG_ENV_IS_IN_NAND		1
#define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */

#define CONFIG_SYS_ENV_SECT_SIZE	(128 << 10)	/* 128 KiB */
#define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET
#define CONFIG_ENV_ADDR			SMNAND_ENV_OFFSET

/*-----------------------------------------------------------------------
 * CFI FLASH driver setup
 */
/* timeout values are in ticks */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(100 * CONFIG_SYS_HZ)
#define CONFIG_SYS_FLASH_WRITE_TOUT	(100 * CONFIG_SYS_HZ)

/* Flash banks JFFS2 should use */
#define CONFIG_SYS_MAX_MTD_BANKS	(CONFIG_SYS_MAX_FLASH_BANKS + \
					CONFIG_SYS_MAX_NAND_DEVICE)
#define CONFIG_SYS_JFFS2_MEM_NAND
/* use flash_info[2] */
#define CONFIG_SYS_JFFS2_FIRST_BANK	CONFIG_SYS_MAX_FLASH_BANKS
#define CONFIG_SYS_JFFS2_NUM_BANKS	1

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR	0x4020f800
#define CONFIG_SYS_INIT_RAM_SIZE	0x800
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - \
					 GENERATED_GBL_DATA_SIZE)

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x40200800
#define CONFIG_SPL_MAX_SIZE		(54 * 1024)	/* 8 KB for stack */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK

#define CONFIG_SPL_BSS_START_ADDR	0x80000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KB */

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300 /* address 0x60000 */
#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS	0x200 /* 256 KB */
#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION	1
#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME	"u-boot.img"

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_FAT_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/omap-common/u-boot-spl.lds"

/* NAND boot config */
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS		{2, 3, 4, 5, 6, 7, 8, 9,\
						10, 11, 12, 13}
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_U_BOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x80000

/*
 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
 * 64 bytes before this address should be set aside for u-boot.img's
 * header. That is 0x800FFFC0--0x80100000 should not be used for any
 * other needs.
 */
#define CONFIG_SYS_TEXT_BASE		0x80100000
#define CONFIG_SYS_SPL_MALLOC_START	0x80208000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x100000

#endif /* __CONFIG_H */
Commit	Line	Data
ed01e45c VH	1	/*
	2	* am3517_evm.h - Default configuration for AM3517 EVM board.
	3	*
	4	* Author: Vaibhav Hiremath <hvaibhav@ti.com>
	5	*
	6	* Based on omap3_evm_config.h
	7	*
	8	* Copyright (C) 2010 Texas Instruments Incorporated
	9	*
1a459660	10	* SPDX-License-Identifier: GPL-2.0+
ed01e45c VH	11	*/
	12
	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
ed01e45c VH	19	#define CONFIG_OMAP 1 /* in a TI OMAP core */
	20	#define CONFIG_OMAP34XX 1 /* which is a 34XX */
	21	#define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */
	22
1a5038ca	23	#define CONFIG_EMIF4 /* The chip has EMIF4 controller */
ed01e45c VH	24
	25	#include <asm/arch/cpu.h> /* get chip and board defs */
	26	#include <asm/arch/omap3.h>
	27
	28	/*
	29	* Display CPU and Board information
	30	*/
	31	#define CONFIG_DISPLAY_CPUINFO 1
	32	#define CONFIG_DISPLAY_BOARDINFO 1
	33
	34	/* Clock Defines */
	35	#define V_OSCK 26000000 /* Clock output from T2 */
	36	#define V_SCLK (V_OSCK >> 1)
	37
ed01e45c VH	38	#define CONFIG_MISC_INIT_R
	39
	40	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	41	#define CONFIG_SETUP_MEMORY_TAGS 1
	42	#define CONFIG_INITRD_TAG 1
	43	#define CONFIG_REVISION_TAG 1
	44
	45	/*
	46	* Size of malloc() pool
	47	*/
	48	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */
	49	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
ed01e45c VH	50	/*
	51	* DDR related
	52	*/
ed01e45c VH	53	#define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
	54
	55	/*
	56	* Hardware drivers
	57	*/
	58
	59	/*
	60	* NS16550 Configuration
	61	*/
	62	#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
	63
	64	#define CONFIG_SYS_NS16550
	65	#define CONFIG_SYS_NS16550_SERIAL
	66	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	67	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	68
	69	/*
	70	* select serial console configuration
	71	*/
	72	#define CONFIG_CONS_INDEX 3
	73	#define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
	74	#define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */
	75
	76	/* allow to overwrite serial and ethaddr */
	77	#define CONFIG_ENV_OVERWRITE
	78	#define CONFIG_BAUDRATE 115200
	79	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	80	115200}
	81	#define CONFIG_MMC 1
122e6e0a VH	82	#define CONFIG_GENERIC_MMC 1
122e6e0a VH	83	#define CONFIG_OMAP_HSMMC 1
ed01e45c VH	84	#define CONFIG_DOS_PARTITION 1
ed01e45c VH	85
7dc27b05 AKG	86	/*
7dc27b05 AKG	87	* USB configuration
88919ff7 IY	88	* Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard
88919ff7 IY	89	* Enable CONFIG_MUSB_GADGET for Device functionalities.
7dc27b05	90	*/
88919ff7 IY	91	#define CONFIG_USB_MUSB_AM35X
	92	#define CONFIG_MUSB_HOST
	93	#define CONFIG_MUSB_PIO_ONLY
7dc27b05	94
88919ff7	95	#ifdef CONFIG_USB_MUSB_AM35X
7dc27b05	96
88919ff7	97	#ifdef CONFIG_MUSB_HOST
7dc27b05 AKG	98	#define CONFIG_CMD_USB
	99
	100	#define CONFIG_USB_STORAGE
	101	#define CONGIG_CMD_STORAGE
	102	#define CONFIG_CMD_FAT
	103
	104	#ifdef CONFIG_USB_KEYBOARD
	105	#define CONFIG_SYS_USB_EVENT_POLL
	106	#define CONFIG_PREBOOT "usb start"
	107	#endif /* CONFIG_USB_KEYBOARD */
	108
88919ff7 IY	109	#endif /* CONFIG_MUSB_HOST */
	110
	111	#ifdef CONFIG_MUSB_GADGET
	112	#define CONFIG_USB_GADGET_DUALSPEED
	113	#define CONFIG_USB_ETHER
	114	#define CONFIG_USB_ETH_RNDIS
	115	#endif /* CONFIG_MUSB_GADGET */
	116
	117	#endif /* CONFIG_USB_MUSB_AM35X */
7dc27b05	118
ed01e45c VH	119	/* commands to include */
	120	#include <config_cmd_default.h>
	121
	122	#define CONFIG_CMD_EXT2 /* EXT2 Support */
	123	#define CONFIG_CMD_FAT /* FAT support */
	124	#define CONFIG_CMD_JFFS2 /* JFFS2 Support */
	125
	126	#define CONFIG_CMD_I2C /* I2C serial bus support */
	127	#define CONFIG_CMD_MMC /* MMC support */
	128	#define CONFIG_CMD_NAND /* NAND support */
	129	#define CONFIG_CMD_DHCP
80615006	130	#undef CONFIG_CMD_PING
ed01e45c VH	131
	132	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	133	#undef CONFIG_CMD_FPGA /* FPGA configuration Support */
	134	#undef CONFIG_CMD_IMI /* iminfo */
	135	#undef CONFIG_CMD_IMLS /* List all found images */
	136
	137	#define CONFIG_SYS_NO_FLASH
	138	#define CONFIG_HARD_I2C 1
	139	#define CONFIG_SYS_I2C_SPEED 100000
	140	#define CONFIG_SYS_I2C_SLAVE 1
ed01e45c VH	141	#define CONFIG_DRIVER_OMAP34XX_I2C 1
	142
	143	#undef CONFIG_CMD_NET
aa82d5f2	144	#undef CONFIG_CMD_NFS
ed01e45c VH	145	/*
	146	* Board NAND Info.
	147	*/
	148	#define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
	149	/* to access nand */
	150	#define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
	151	/* to access */
	152	/* nand at CS0 */
	153
	154	#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
	155	/* NAND devices */
ed01e45c VH	156	#define CONFIG_JFFS2_NAND
	157	/* nand device jffs2 lives on */
	158	#define CONFIG_JFFS2_DEV "nand0"
	159	/* start of jffs2 partition */
	160	#define CONFIG_JFFS2_PART_OFFSET 0x680000
	161	#define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
	162
	163	/* Environment information */
	164	#define CONFIG_BOOTDELAY 10
	165
b3f44c21	166	#define CONFIG_BOOTFILE "uImage"
ed01e45c VH	167
	168	#define CONFIG_EXTRA_ENV_SETTINGS \
	169	"loadaddr=0x82000000\0" \
49473ada	170	"console=ttyO2,115200n8\0" \
122e6e0a	171	"mmcdev=0\0" \
ed01e45c	172	"mmcargs=setenv bootargs console=${console} " \
10f3bdd3	173	"root=/dev/mmcblk0p2 rw rootwait\0" \
ed01e45c VH	174	"nandargs=setenv bootargs console=${console} " \
	175	"root=/dev/mtdblock4 rw " \
	176	"rootfstype=jffs2\0" \
122e6e0a	177	"loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
ed01e45c VH	178	"bootscript=echo Running bootscript from mmc ...; " \
ed01e45c VH	179	"source ${loadaddr}\0" \
122e6e0a	180	"loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
ed01e45c VH	181	"mmcboot=echo Booting from mmc ...; " \
	182	"run mmcargs; " \
	183	"bootm ${loadaddr}\0" \
	184	"nandboot=echo Booting from nand ...; " \
	185	"run nandargs; " \
	186	"nand read ${loadaddr} 280000 400000; " \
	187	"bootm ${loadaddr}\0" \
	188
	189	#define CONFIG_BOOTCOMMAND \
66968110	190	"mmc dev ${mmcdev}; if mmc rescan; then " \
ed01e45c VH	191	"if run loadbootscript; then " \
	192	"run bootscript; " \
	193	"else " \
	194	"if run loaduimage; then " \
	195	"run mmcboot; " \
	196	"else run nandboot; " \
	197	"fi; " \
	198	"fi; " \
	199	"else run nandboot; fi"
	200
	201	#define CONFIG_AUTO_COMPLETE 1
	202	/*
	203	* Miscellaneous configurable options
	204	*/
	205	#define V_PROMPT "AM3517_EVM # "
	206
	207	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	208	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
ed01e45c VH	209	#define CONFIG_SYS_PROMPT V_PROMPT
	210	#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
	211	/* Print Buffer Size */
	212	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	213	sizeof(CONFIG_SYS_PROMPT) + 16)
	214	#define CONFIG_SYS_MAXARGS 32 /* max number of command */
	215	/* args */
	216	/* Boot Argument Buffer Size */
	217	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	218	/* memtest works on */
	219	#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
	220	#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
	221	0x01F00000) /* 31MB */
	222
	223	#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
	224	/* address */
	225
	226	/*
	227	* AM3517 has 12 GP timers, they can be driven by the system clock
	228	* (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
	229	* This rate is divided by a local divisor.
	230	*/
	231	#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
	232	#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
	233	#define CONFIG_SYS_HZ 1000
	234
ed01e45c VH	235	/*-----------------------------------------------------------------------
	236	* Physical Memory Map
	237	*/
	238	#define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
	239	#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
ed01e45c VH	240	#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
ed01e45c VH	241
ed01e45c VH	242	/*-----------------------------------------------------------------------
	243	* FLASH and environment organization
	244	*/
	245
	246	/* ** PISMO SUPPORT * */
	247
	248	/* Configure the PISMO */
	249	#define PISMO1_NAND_SIZE GPMC_SIZE_128M
	250	#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
	251
	252	#define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
	253	/* on one chip */
	254	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
	255	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	256
6cbec7b3 LC	257	#if defined(CONFIG_CMD_NAND)
	258	#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
	259	#endif
ed01e45c VH	260
	261	/* Monitor at start of flash */
	262	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	263
	264	#define CONFIG_NAND_OMAP_GPMC
	265	#define GPMC_NAND_ECC_LP_x16_LAYOUT 1
	266	#define CONFIG_ENV_IS_IN_NAND 1
	267	#define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
	268
6cbec7b3 LC	269	#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
	270	#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
	271	#define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
ed01e45c VH	272
	273	/*-----------------------------------------------------------------------
	274	* CFI FLASH driver setup
	275	*/
	276	/* timeout values are in ticks */
	277	#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
	278	#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
	279
	280	/* Flash banks JFFS2 should use */
	281	#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
	282	CONFIG_SYS_MAX_NAND_DEVICE)
	283	#define CONFIG_SYS_JFFS2_MEM_NAND
	284	/* use flash_info[2] */
	285	#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
	286	#define CONFIG_SYS_JFFS2_NUM_BANKS 1
	287
13acfc6f VH	288	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
	289	#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
	290	#define CONFIG_SYS_INIT_RAM_SIZE 0x800
	291	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	292	CONFIG_SYS_INIT_RAM_SIZE - \
	293	GENERATED_GBL_DATA_SIZE)
5059a2a4 TR	294
	295	/* Defines for SPL */
	296	#define CONFIG_SPL
47f7bcae	297	#define CONFIG_SPL_FRAMEWORK
d7cb93b2	298	#define CONFIG_SPL_BOARD_INIT
5059a2a4 TR	299	#define CONFIG_SPL_NAND_SIMPLE
5059a2a4 TR	300	#define CONFIG_SPL_TEXT_BASE 0x40200800
e0820ccc	301	#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
5059a2a4 TR	302	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	303
	304	#define CONFIG_SPL_BSS_START_ADDR 0x80000000
	305	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
	306
	307	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */
	308	#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */
	309	#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1
	310	#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img"
	311
	312	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	313	#define CONFIG_SPL_LIBDISK_SUPPORT
	314	#define CONFIG_SPL_I2C_SUPPORT
	315	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	316	#define CONFIG_SPL_MMC_SUPPORT
	317	#define CONFIG_SPL_FAT_SUPPORT
	318	#define CONFIG_SPL_SERIAL_SUPPORT
	319	#define CONFIG_SPL_NAND_SUPPORT
6f2f01b9 SW	320	#define CONFIG_SPL_NAND_BASE
	321	#define CONFIG_SPL_NAND_DRIVERS
	322	#define CONFIG_SPL_NAND_ECC
5059a2a4 TR	323	#define CONFIG_SPL_POWER_SUPPORT
	324	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
	325
	326	/* NAND boot config */
	327	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	328	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	329	#define CONFIG_SYS_NAND_PAGE_SIZE 2048
	330	#define CONFIG_SYS_NAND_OOBSIZE 64
	331	#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
	332	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	333	#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
	334	10, 11, 12, 13}
	335	#define CONFIG_SYS_NAND_ECCSIZE 512
	336	#define CONFIG_SYS_NAND_ECCBYTES 3
5059a2a4 TR	337	#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
	338	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
	339
	340	/*
	341	* 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
	342	* 64 bytes before this address should be set aside for u-boot.img's
	343	* header. That is 0x800FFFC0--0x80100000 should not be used for any
	344	* other needs.
	345	*/
	346	#define CONFIG_SYS_TEXT_BASE 0x80100000
	347	#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
	348	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
	349
ed01e45c	350	#endif /* __CONFIG_H */