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ed01e45c VH |
1 | /* |
2 | * am3517_evm.h - Default configuration for AM3517 EVM board. | |
3 | * | |
4 | * Author: Vaibhav Hiremath <hvaibhav@ti.com> | |
5 | * | |
6 | * Based on omap3_evm_config.h | |
7 | * | |
8 | * Copyright (C) 2010 Texas Instruments Incorporated | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
ed01e45c VH |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
ed01e45c VH |
19 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
20 | #define CONFIG_OMAP34XX 1 /* which is a 34XX */ | |
21 | #define CONFIG_OMAP3_AM3517EVM 1 /* working with AM3517EVM */ | |
806d2792 | 22 | #define CONFIG_OMAP_COMMON |
ed01e45c | 23 | |
1a5038ca | 24 | #define CONFIG_EMIF4 /* The chip has EMIF4 controller */ |
ed01e45c VH |
25 | |
26 | #include <asm/arch/cpu.h> /* get chip and board defs */ | |
27 | #include <asm/arch/omap3.h> | |
28 | ||
29 | /* | |
30 | * Display CPU and Board information | |
31 | */ | |
32 | #define CONFIG_DISPLAY_CPUINFO 1 | |
33 | #define CONFIG_DISPLAY_BOARDINFO 1 | |
34 | ||
35 | /* Clock Defines */ | |
36 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
37 | #define V_SCLK (V_OSCK >> 1) | |
38 | ||
ed01e45c VH |
39 | #define CONFIG_MISC_INIT_R |
40 | ||
41 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
42 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
43 | #define CONFIG_INITRD_TAG 1 | |
44 | #define CONFIG_REVISION_TAG 1 | |
45 | ||
46 | /* | |
47 | * Size of malloc() pool | |
48 | */ | |
49 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
50 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10)) | |
ed01e45c VH |
51 | /* |
52 | * DDR related | |
53 | */ | |
ed01e45c VH |
54 | #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024) |
55 | ||
56 | /* | |
57 | * Hardware drivers | |
58 | */ | |
59 | ||
60 | /* | |
61 | * NS16550 Configuration | |
62 | */ | |
63 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
64 | ||
65 | #define CONFIG_SYS_NS16550 | |
66 | #define CONFIG_SYS_NS16550_SERIAL | |
67 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
68 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
69 | ||
70 | /* | |
71 | * select serial console configuration | |
72 | */ | |
73 | #define CONFIG_CONS_INDEX 3 | |
74 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
75 | #define CONFIG_SERIAL3 3 /* UART3 on AM3517 EVM */ | |
76 | ||
77 | /* allow to overwrite serial and ethaddr */ | |
78 | #define CONFIG_ENV_OVERWRITE | |
79 | #define CONFIG_BAUDRATE 115200 | |
80 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ | |
81 | 115200} | |
82 | #define CONFIG_MMC 1 | |
122e6e0a VH |
83 | #define CONFIG_GENERIC_MMC 1 |
84 | #define CONFIG_OMAP_HSMMC 1 | |
ed01e45c VH |
85 | #define CONFIG_DOS_PARTITION 1 |
86 | ||
7dc27b05 AKG |
87 | /* |
88 | * USB configuration | |
88919ff7 IY |
89 | * Enable CONFIG_MUSB_HOST for Host functionalities MSC, keyboard |
90 | * Enable CONFIG_MUSB_GADGET for Device functionalities. | |
7dc27b05 | 91 | */ |
88919ff7 IY |
92 | #define CONFIG_USB_MUSB_AM35X |
93 | #define CONFIG_MUSB_HOST | |
94 | #define CONFIG_MUSB_PIO_ONLY | |
7dc27b05 | 95 | |
88919ff7 | 96 | #ifdef CONFIG_USB_MUSB_AM35X |
7dc27b05 | 97 | |
88919ff7 | 98 | #ifdef CONFIG_MUSB_HOST |
7dc27b05 AKG |
99 | #define CONFIG_CMD_USB |
100 | ||
101 | #define CONFIG_USB_STORAGE | |
102 | #define CONGIG_CMD_STORAGE | |
103 | #define CONFIG_CMD_FAT | |
104 | ||
105 | #ifdef CONFIG_USB_KEYBOARD | |
106 | #define CONFIG_SYS_USB_EVENT_POLL | |
107 | #define CONFIG_PREBOOT "usb start" | |
108 | #endif /* CONFIG_USB_KEYBOARD */ | |
109 | ||
88919ff7 IY |
110 | #endif /* CONFIG_MUSB_HOST */ |
111 | ||
112 | #ifdef CONFIG_MUSB_GADGET | |
113 | #define CONFIG_USB_GADGET_DUALSPEED | |
114 | #define CONFIG_USB_ETHER | |
115 | #define CONFIG_USB_ETH_RNDIS | |
116 | #endif /* CONFIG_MUSB_GADGET */ | |
117 | ||
118 | #endif /* CONFIG_USB_MUSB_AM35X */ | |
7dc27b05 | 119 | |
ed01e45c VH |
120 | /* commands to include */ |
121 | #include <config_cmd_default.h> | |
122 | ||
123 | #define CONFIG_CMD_EXT2 /* EXT2 Support */ | |
124 | #define CONFIG_CMD_FAT /* FAT support */ | |
125 | #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ | |
126 | ||
127 | #define CONFIG_CMD_I2C /* I2C serial bus support */ | |
128 | #define CONFIG_CMD_MMC /* MMC support */ | |
129 | #define CONFIG_CMD_NAND /* NAND support */ | |
130 | #define CONFIG_CMD_DHCP | |
80615006 | 131 | #undef CONFIG_CMD_PING |
ed01e45c VH |
132 | |
133 | #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */ | |
134 | #undef CONFIG_CMD_FPGA /* FPGA configuration Support */ | |
135 | #undef CONFIG_CMD_IMI /* iminfo */ | |
136 | #undef CONFIG_CMD_IMLS /* List all found images */ | |
137 | ||
138 | #define CONFIG_SYS_NO_FLASH | |
6789e84e HS |
139 | #define CONFIG_SYS_I2C |
140 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
141 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
142 | #define CONFIG_SYS_I2C_OMAP34XX | |
ed01e45c | 143 | |
18a02e80 TR |
144 | /* |
145 | * Ethernet | |
146 | */ | |
147 | #define CONFIG_DRIVER_TI_EMAC | |
148 | #define CONFIG_DRIVER_TI_EMAC_USE_RMII | |
149 | #define CONFIG_MII | |
150 | #define CONFIG_BOOTP_DEFAULT | |
151 | #define CONFIG_BOOTP_DNS | |
152 | #define CONFIG_BOOTP_DNS2 | |
153 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
154 | #define CONFIG_NET_RETRY_COUNT 10 | |
155 | ||
ed01e45c VH |
156 | /* |
157 | * Board NAND Info. | |
158 | */ | |
159 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ | |
160 | /* to access nand */ | |
161 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
162 | /* to access */ | |
163 | /* nand at CS0 */ | |
164 | ||
165 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ | |
166 | /* NAND devices */ | |
ed01e45c VH |
167 | #define CONFIG_JFFS2_NAND |
168 | /* nand device jffs2 lives on */ | |
169 | #define CONFIG_JFFS2_DEV "nand0" | |
170 | /* start of jffs2 partition */ | |
171 | #define CONFIG_JFFS2_PART_OFFSET 0x680000 | |
172 | #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */ | |
173 | ||
174 | /* Environment information */ | |
175 | #define CONFIG_BOOTDELAY 10 | |
176 | ||
b3f44c21 | 177 | #define CONFIG_BOOTFILE "uImage" |
ed01e45c VH |
178 | |
179 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
180 | "loadaddr=0x82000000\0" \ | |
49473ada | 181 | "console=ttyO2,115200n8\0" \ |
122e6e0a | 182 | "mmcdev=0\0" \ |
ed01e45c | 183 | "mmcargs=setenv bootargs console=${console} " \ |
10f3bdd3 | 184 | "root=/dev/mmcblk0p2 rw rootwait\0" \ |
ed01e45c VH |
185 | "nandargs=setenv bootargs console=${console} " \ |
186 | "root=/dev/mtdblock4 rw " \ | |
187 | "rootfstype=jffs2\0" \ | |
122e6e0a | 188 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ |
ed01e45c VH |
189 | "bootscript=echo Running bootscript from mmc ...; " \ |
190 | "source ${loadaddr}\0" \ | |
122e6e0a | 191 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ |
ed01e45c VH |
192 | "mmcboot=echo Booting from mmc ...; " \ |
193 | "run mmcargs; " \ | |
194 | "bootm ${loadaddr}\0" \ | |
195 | "nandboot=echo Booting from nand ...; " \ | |
196 | "run nandargs; " \ | |
197 | "nand read ${loadaddr} 280000 400000; " \ | |
198 | "bootm ${loadaddr}\0" \ | |
199 | ||
200 | #define CONFIG_BOOTCOMMAND \ | |
66968110 | 201 | "mmc dev ${mmcdev}; if mmc rescan; then " \ |
ed01e45c VH |
202 | "if run loadbootscript; then " \ |
203 | "run bootscript; " \ | |
204 | "else " \ | |
205 | "if run loaduimage; then " \ | |
206 | "run mmcboot; " \ | |
207 | "else run nandboot; " \ | |
208 | "fi; " \ | |
209 | "fi; " \ | |
210 | "else run nandboot; fi" | |
211 | ||
212 | #define CONFIG_AUTO_COMPLETE 1 | |
213 | /* | |
214 | * Miscellaneous configurable options | |
215 | */ | |
216 | #define V_PROMPT "AM3517_EVM # " | |
217 | ||
218 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
219 | #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ | |
ed01e45c VH |
220 | #define CONFIG_SYS_PROMPT V_PROMPT |
221 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
222 | /* Print Buffer Size */ | |
223 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
224 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
225 | #define CONFIG_SYS_MAXARGS 32 /* max number of command */ | |
226 | /* args */ | |
227 | /* Boot Argument Buffer Size */ | |
228 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
229 | /* memtest works on */ | |
230 | #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) | |
231 | #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \ | |
232 | 0x01F00000) /* 31MB */ | |
233 | ||
234 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */ | |
235 | /* address */ | |
236 | ||
237 | /* | |
238 | * AM3517 has 12 GP timers, they can be driven by the system clock | |
239 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
240 | * This rate is divided by a local divisor. | |
241 | */ | |
242 | #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2 | |
243 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
ed01e45c | 244 | |
ed01e45c VH |
245 | /*----------------------------------------------------------------------- |
246 | * Physical Memory Map | |
247 | */ | |
248 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
249 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
ed01e45c VH |
250 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 |
251 | ||
ed01e45c VH |
252 | /*----------------------------------------------------------------------- |
253 | * FLASH and environment organization | |
254 | */ | |
255 | ||
256 | /* **** PISMO SUPPORT *** */ | |
257 | ||
258 | /* Configure the PISMO */ | |
259 | #define PISMO1_NAND_SIZE GPMC_SIZE_128M | |
260 | #define PISMO1_ONEN_SIZE GPMC_SIZE_128M | |
261 | ||
262 | #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */ | |
263 | /* on one chip */ | |
264 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */ | |
265 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ | |
266 | ||
6cbec7b3 LC |
267 | #if defined(CONFIG_CMD_NAND) |
268 | #define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE | |
269 | #endif | |
ed01e45c VH |
270 | |
271 | /* Monitor at start of flash */ | |
272 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
273 | ||
274 | #define CONFIG_NAND_OMAP_GPMC | |
275 | #define GPMC_NAND_ECC_LP_x16_LAYOUT 1 | |
276 | #define CONFIG_ENV_IS_IN_NAND 1 | |
277 | #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */ | |
278 | ||
6cbec7b3 LC |
279 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ |
280 | #define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET | |
281 | #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET | |
ed01e45c VH |
282 | |
283 | /*----------------------------------------------------------------------- | |
284 | * CFI FLASH driver setup | |
285 | */ | |
286 | /* timeout values are in ticks */ | |
287 | #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ) | |
288 | #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ) | |
289 | ||
290 | /* Flash banks JFFS2 should use */ | |
291 | #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \ | |
292 | CONFIG_SYS_MAX_NAND_DEVICE) | |
293 | #define CONFIG_SYS_JFFS2_MEM_NAND | |
294 | /* use flash_info[2] */ | |
295 | #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS | |
296 | #define CONFIG_SYS_JFFS2_NUM_BANKS 1 | |
297 | ||
13acfc6f VH |
298 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
299 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
300 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
301 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
302 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
303 | GENERATED_GBL_DATA_SIZE) | |
5059a2a4 TR |
304 | |
305 | /* Defines for SPL */ | |
306 | #define CONFIG_SPL | |
47f7bcae | 307 | #define CONFIG_SPL_FRAMEWORK |
d7cb93b2 | 308 | #define CONFIG_SPL_BOARD_INIT |
5059a2a4 TR |
309 | #define CONFIG_SPL_NAND_SIMPLE |
310 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
e0820ccc | 311 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */ |
5059a2a4 TR |
312 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
313 | ||
314 | #define CONFIG_SPL_BSS_START_ADDR 0x80000000 | |
315 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
316 | ||
317 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ | |
318 | #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ | |
319 | #define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 | |
320 | #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" | |
321 | ||
322 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
323 | #define CONFIG_SPL_LIBDISK_SUPPORT | |
324 | #define CONFIG_SPL_I2C_SUPPORT | |
325 | #define CONFIG_SPL_LIBGENERIC_SUPPORT | |
326 | #define CONFIG_SPL_MMC_SUPPORT | |
327 | #define CONFIG_SPL_FAT_SUPPORT | |
328 | #define CONFIG_SPL_SERIAL_SUPPORT | |
329 | #define CONFIG_SPL_NAND_SUPPORT | |
6f2f01b9 SW |
330 | #define CONFIG_SPL_NAND_BASE |
331 | #define CONFIG_SPL_NAND_DRIVERS | |
332 | #define CONFIG_SPL_NAND_ECC | |
5059a2a4 TR |
333 | #define CONFIG_SPL_POWER_SUPPORT |
334 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
335 | ||
336 | /* NAND boot config */ | |
337 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
338 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
339 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
340 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
341 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) | |
342 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
343 | #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ | |
344 | 10, 11, 12, 13} | |
345 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
346 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
3f719069 | 347 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW |
5059a2a4 TR |
348 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
349 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
350 | ||
351 | /* | |
352 | * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM | |
353 | * 64 bytes before this address should be set aside for u-boot.img's | |
354 | * header. That is 0x800FFFC0--0x80100000 should not be used for any | |
355 | * other needs. | |
356 | */ | |
357 | #define CONFIG_SYS_TEXT_BASE 0x80100000 | |
358 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
359 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
360 | ||
ed01e45c | 361 | #endif /* __CONFIG_H */ |