| 06fd66a4 |
1 | /* |
| 2 | * Sysam AMCORE board configuration |
| 3 | * |
| 4 | * (C) Copyright 2015 Angelo Dureghello <angelo@sysam.it> |
| 5 | * |
| 6 | * SPDX-License-Identifier: GPL-2.0+ |
| 7 | */ |
| 8 | |
| 9 | #ifndef __AMCORE_CONFIG_H |
| 10 | #define __AMCORE_CONFIG_H |
| 11 | |
| 12 | #define CONFIG_AMCORE |
| 13 | #define CONFIG_HOSTNAME AMCORE |
| 14 | |
| 06fd66a4 |
15 | #define CONFIG_MCF530x |
| 16 | #define CONFIG_M5307 |
| 17 | |
| 18 | #define CONFIG_MCFTMR |
| 19 | #define CONFIG_MCFUART |
| 20 | #define CONFIG_SYS_UART_PORT 0 |
| 21 | #define CONFIG_BAUDRATE 115200 |
| 22 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
| 23 | |
| 24 | #define CONFIG_BOOTDELAY 1 |
| 25 | #define CONFIG_BOOTCOMMAND "bootm ffc20000" |
| 26 | |
| 27 | #include <config_cmd_default.h> |
| 28 | #undef CONFIG_CMD_AES |
| 29 | #undef CONFIG_CMD_BOOTD |
| 30 | #undef CONFIG_CMD_NET |
| 31 | #undef CONFIG_CMD_NFS |
| 32 | #undef CONFIG_CMD_FPGA |
| 33 | #undef CONFIG_CMD_XIMG |
| 34 | #define CONFIG_CMD_CACHE |
| 35 | #define CONFIG_CMD_TIMER |
| 36 | #define CONFIG_CMD_DIAG |
| 37 | |
| 38 | #define CONFIG_SYS_PROMPT "amcore $ " |
| 39 | /* undef to save memory */ |
| 40 | #undef CONFIG_SYS_LONGHELP |
| 41 | |
| 42 | #if defined(CONFIG_CMD_KGDB) |
| 43 | /* Console I/O buff. size */ |
| 44 | #define CONFIG_SYS_CBSIZE 1024 |
| 45 | #else |
| 46 | #define CONFIG_SYS_CBSIZE 256 |
| 47 | #endif |
| 48 | /* Print buffer size */ |
| 49 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 50 | sizeof(CONFIG_SYS_PROMPT)+16) |
| 51 | /* max number of command args */ |
| 52 | #define CONFIG_SYS_MAXARGS 16 |
| 53 | /* Boot argument buffer size */ |
| 54 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 55 | |
| 56 | #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* no console @ startup */ |
| 57 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
| 58 | #define CONFIG_LOOPW 1 /* enable loopw command */ |
| 59 | #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ |
| 60 | |
| 61 | #define CONFIG_SYS_LOAD_ADDR 0x20000 /* default load address */ |
| 62 | |
| 63 | #define CONFIG_SYS_MEMTEST_START 0x0 |
| 64 | #define CONFIG_SYS_MEMTEST_END 0x1000000 |
| 65 | |
| 66 | #define CONFIG_SYS_HZ 1000 |
| 67 | |
| 68 | #define CONFIG_SYS_CLK 45000000 |
| 69 | #define CONFIG_SYS_CPU_CLK (CONFIG_SYS_CLK * 2) |
| 70 | /* Register Base Addrs */ |
| 71 | #define CONFIG_SYS_MBAR 0x10000000 |
| 72 | /* Definitions for initial stack pointer and data area (in DPRAM) */ |
| 73 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
| 74 | /* size of internal SRAM */ |
| 75 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 |
| 76 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 77 | GENERATED_GBL_DATA_SIZE) |
| 78 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 79 | |
| 80 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 81 | #define CONFIG_SYS_SDRAM_SIZE 0x1000000 |
| 82 | #define CONFIG_SYS_FLASH_BASE 0xffc00000 |
| 83 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
| 84 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 |
| 85 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 |
| 86 | |
| 87 | #define CONFIG_SYS_FLASH_CFI |
| 88 | #define CONFIG_FLASH_CFI_DRIVER |
| 89 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE |
| 90 | /* amcore design has flash data bytes wired swapped */ |
| 91 | #define CONFIG_SYS_WRITE_SWAPPED_DATA |
| 92 | /* reserve 128-4KB */ |
| 93 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 94 | #define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024) |
| 95 | #define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024) |
| 96 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) |
| 97 | |
| 98 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 99 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \ |
| 100 | CONFIG_SYS_MONITOR_LEN) |
| 101 | #define CONFIG_ENV_SIZE 0x1000 |
| 102 | #define CONFIG_ENV_SECT_SIZE 0x1000 |
| 103 | |
| 104 | /* memory map space for linux boot data */ |
| 105 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) |
| 106 | |
| 107 | /* |
| 108 | * Cache Configuration |
| 109 | * |
| 110 | * Special 8K version 3 core cache. |
| 111 | * This is a single unified instruction/data cache. |
| 112 | * sdram - single region - no masks |
| 113 | */ |
| 114 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
| 115 | |
| 116 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 117 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
| 118 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 119 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
| 120 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
| 121 | #define CONFIG_SYS_CACHE_ACR0 (CF_ACR_CM_WT | CF_ACR_SM_ALL | \ |
| 122 | CF_ACR_EN) |
| 123 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_DCM_P | CF_CACR_ESB | \ |
| 124 | CF_CACR_EC) |
| 125 | |
| 126 | /* CS0 - AMD Flash, address 0xffc00000 */ |
| 127 | #define CONFIG_SYS_CS0_BASE (CONFIG_SYS_FLASH_BASE>>16) |
| 128 | /* 4MB, AA=0,V=1 C/I BIT for errata */ |
| 129 | #define CONFIG_SYS_CS0_MASK 0x003f0001 |
| 130 | /* WS=10, AA=1, PS=16bit (10) */ |
| 131 | #define CONFIG_SYS_CS0_CTRL 0x1980 |
| 132 | /* CS1 - DM9000 Ethernet Controller, address 0x30000000 */ |
| 133 | #define CONFIG_SYS_CS1_BASE 0x3000 |
| 134 | #define CONFIG_SYS_CS1_MASK 0x00070001 |
| 135 | #define CONFIG_SYS_CS1_CTRL 0x0100 |
| 136 | |
| 137 | #endif /* __AMCORE_CONFIG_H */ |
| 138 | |
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