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6f0da497 NI |
1 | /* |
2 | * Configuation settings for the Renesas Solutions AP-325RXA board | |
3 | * | |
4 | * Copyright (C) 2008 Renesas Solutions Corp. | |
5 | * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
6f0da497 NI |
8 | */ |
9 | ||
10 | #ifndef __AP325RXA_H | |
11 | #define __AP325RXA_H | |
12 | ||
6f0da497 NI |
13 | #define CONFIG_CPU_SH7723 1 |
14 | #define CONFIG_AP325RXA 1 | |
15 | ||
18a40e84 | 16 | #define CONFIG_DISPLAY_BOARDINFO |
6f0da497 NI |
17 | #undef CONFIG_SHOW_BOOT_PROGRESS |
18 | ||
19 | /* SMC9118 */ | |
736fead8 BW |
20 | #define CONFIG_SMC911X 1 |
21 | #define CONFIG_SMC911X_32_BIT 1 | |
22 | #define CONFIG_SMC911X_BASE 0xB6080000 | |
6f0da497 NI |
23 | |
24 | /* MEMORY */ | |
25 | #define AP325RXA_SDRAM_BASE (0x88000000) | |
26 | #define AP325RXA_FLASH_BASE_1 (0xA0000000) | |
27 | #define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024) | |
28 | ||
db68b703 NI |
29 | #define CONFIG_SYS_TEXT_BASE 0x8FFC0000 |
30 | ||
6f0da497 | 31 | /* undef to save memory */ |
6d0f6bcf | 32 | #define CONFIG_SYS_LONGHELP |
6f0da497 | 33 | /* Monitor Command Prompt */ |
6f0da497 | 34 | /* Buffer size for Console output */ |
6d0f6bcf | 35 | #define CONFIG_SYS_PBSIZE 256 |
6f0da497 | 36 | /* Buffer size for Boot Arguments passed to kernel */ |
6d0f6bcf | 37 | #define CONFIG_SYS_BARGSIZE 512 |
6f0da497 | 38 | /* List of legal baudrate settings for this board */ |
6d0f6bcf | 39 | #define CONFIG_SYS_BAUDRATE_TABLE { 38400 } |
6f0da497 NI |
40 | |
41 | /* SCIF */ | |
6f0da497 NI |
42 | #define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ |
43 | #define CONFIG_CONS_SCIF5 1 | |
44 | ||
45 | /* Suppress display of console information at boot */ | |
6f0da497 | 46 | |
6d0f6bcf JCPV |
47 | #define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE) |
48 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) | |
6f0da497 NI |
49 | |
50 | /* Enable alternate, more extensive, memory test */ | |
6d0f6bcf | 51 | #undef CONFIG_SYS_ALT_MEMTEST |
6f0da497 | 52 | /* Scratch address used by the alternate memory test */ |
6d0f6bcf | 53 | #undef CONFIG_SYS_MEMTEST_SCRATCH |
6f0da497 NI |
54 | |
55 | /* Enable temporary baudrate change while serial download */ | |
6d0f6bcf | 56 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE |
6f0da497 | 57 | |
6d0f6bcf | 58 | #define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE) |
6f0da497 | 59 | /* maybe more, but if so u-boot doesn't know about it... */ |
6d0f6bcf | 60 | #define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) |
6f0da497 | 61 | /* default load address for scripts ?!? */ |
6d0f6bcf | 62 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) |
6f0da497 NI |
63 | |
64 | /* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ | |
6d0f6bcf | 65 | #define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1) |
6f0da497 | 66 | /* Monitor size */ |
6d0f6bcf | 67 | #define CONFIG_SYS_MONITOR_LEN (128 * 1024) |
6f0da497 | 68 | /* Size of DRAM reserved for malloc() use */ |
6d0f6bcf | 69 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) |
6d0f6bcf | 70 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
6f0da497 NI |
71 | |
72 | /* FLASH */ | |
73 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
6d0f6bcf JCPV |
74 | #define CONFIG_SYS_FLASH_CFI |
75 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
6f0da497 | 76 | /* print 'E' for empty sector on flinfo */ |
6d0f6bcf | 77 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
6f0da497 | 78 | /* Physical start address of Flash memory */ |
6d0f6bcf | 79 | #define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1) |
6f0da497 | 80 | /* Max number of sectors on each Flash chip */ |
6d0f6bcf | 81 | #define CONFIG_SYS_MAX_FLASH_SECT 512 |
6f0da497 NI |
82 | |
83 | /* | |
84 | * IDE support | |
85 | */ | |
86 | #define CONFIG_IDE_RESET 1 | |
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_PIO_MODE 1 |
88 | #define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ | |
89 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
90 | #define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000 | |
91 | #define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ | |
92 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */ | |
93 | #define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */ | |
94 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */ | |
f2a37fcd | 95 | #define CONFIG_IDE_SWAP_IO |
6f0da497 NI |
96 | |
97 | /* if you use all NOR Flash , you change dip-switch. Please see Manual. */ | |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
99 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)} | |
6f0da497 NI |
100 | |
101 | /* Timeout for Flash erase operations (in ms) */ | |
6d0f6bcf | 102 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
6f0da497 | 103 | /* Timeout for Flash write operations (in ms) */ |
6d0f6bcf | 104 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) |
6f0da497 | 105 | /* Timeout for Flash set sector lock bit operations (in ms) */ |
6d0f6bcf | 106 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) |
6f0da497 | 107 | /* Timeout for Flash clear lock bit operations (in ms) */ |
6d0f6bcf | 108 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) |
6f0da497 NI |
109 | |
110 | /* | |
111 | * Use hardware flash sectors protection instead | |
112 | * of U-Boot software protection | |
113 | */ | |
6d0f6bcf JCPV |
114 | #undef CONFIG_SYS_FLASH_PROTECTION |
115 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
6f0da497 NI |
116 | |
117 | /* ENV setting */ | |
6f0da497 | 118 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
119 | #define CONFIG_ENV_SECT_SIZE (128 * 1024) |
120 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
121 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
122 | /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ | |
123 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 124 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
6f0da497 NI |
125 | |
126 | /* Board Clock */ | |
127 | #define CONFIG_SYS_CLK_FREQ 33333333 | |
684a501e NI |
128 | #define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ |
129 | #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
be45c632 | 130 | #define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */ |
6f0da497 NI |
131 | |
132 | #endif /* __AP325RXA_H */ |