[people/ms/u-boot.git] / include / configs / ap325rxa.h

/*
 * Configuation settings for the Renesas Solutions AP-325RXA board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __AP325RXA_H
#define __AP325RXA_H

#undef DEBUG
#define CONFIG_CPU_SH7723	1
#define CONFIG_AP325RXA	1

#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_IDE
#define CONFIG_CMD_EXT2
#define CONFIG_DOS_PARTITION

#define CONFIG_BAUDRATE		38400
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTARGS		"console=ttySC2,38400"

#define CONFIG_VERSION_VARIABLE
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SMC9118 */
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT 1
#define CONFIG_SMC911X_BASE 0xB6080000

/* MEMORY */
#define AP325RXA_SDRAM_BASE		(0x88000000)
#define AP325RXA_FLASH_BASE_1		(0xA0000000)
#define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000

/* undef to save memory	*/
#define CONFIG_SYS_LONGHELP
/* Monitor Command Prompt */
/* Buffer size for input from the Console */
#define CONFIG_SYS_CBSIZE		256
/* Buffer size for Console output */
#define CONFIG_SYS_PBSIZE		256
/* max args accepted for monitor commands */
#define CONFIG_SYS_MAXARGS		16
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE	512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF_A		1 /* SH7723 has SCIF and SCIFA */
#define CONFIG_CONS_SCIF5	1

/* Suppress display of console information at boot */
#undef  CONFIG_SYS_CONSOLE_INFO_QUIET
#undef  CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef  CONFIG_SYS_CONSOLE_ENV_OVERWRITE

#define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
#define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* ENV setting */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#endif	/* __AP325RXA_H */
Commit	Line	Data
6f0da497 NI	1	/*
	2	* Configuation settings for the Renesas Solutions AP-325RXA board
	3	*
	4	* Copyright (C) 2008 Renesas Solutions Corp.
	5	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
6f0da497 NI	8	*/
	9
	10	#ifndef __AP325RXA_H
	11	#define __AP325RXA_H
	12
	13	#undef DEBUG
6f0da497 NI	14	#define CONFIG_CPU_SH7723 1
	15	#define CONFIG_AP325RXA 1
	16
6f0da497	17	#define CONFIG_CMD_SDRAM
6f0da497 NI	18	#define CONFIG_CMD_IDE
	19	#define CONFIG_CMD_EXT2
	20	#define CONFIG_DOS_PARTITION
	21
	22	#define CONFIG_BAUDRATE 38400
	23	#define CONFIG_BOOTDELAY 3
	24	#define CONFIG_BOOTARGS "console=ttySC2,38400"
	25
	26	#define CONFIG_VERSION_VARIABLE
	27	#undef CONFIG_SHOW_BOOT_PROGRESS
	28
	29	/* SMC9118 */
736fead8 BW	30	#define CONFIG_SMC911X 1
	31	#define CONFIG_SMC911X_32_BIT 1
	32	#define CONFIG_SMC911X_BASE 0xB6080000
6f0da497 NI	33
	34	/* MEMORY */
	35	#define AP325RXA_SDRAM_BASE (0x88000000)
	36	#define AP325RXA_FLASH_BASE_1 (0xA0000000)
	37	#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
	38
db68b703 NI	39	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
db68b703 NI	40
6f0da497	41	/* undef to save memory */
6d0f6bcf	42	#define CONFIG_SYS_LONGHELP
6f0da497	43	/* Monitor Command Prompt */
6f0da497	44	/* Buffer size for input from the Console */
6d0f6bcf	45	#define CONFIG_SYS_CBSIZE 256
6f0da497	46	/* Buffer size for Console output */
6d0f6bcf	47	#define CONFIG_SYS_PBSIZE 256
6f0da497	48	/* max args accepted for monitor commands */
6d0f6bcf	49	#define CONFIG_SYS_MAXARGS 16
6f0da497	50	/* Buffer size for Boot Arguments passed to kernel */
6d0f6bcf	51	#define CONFIG_SYS_BARGSIZE 512
6f0da497	52	/* List of legal baudrate settings for this board */
6d0f6bcf	53	#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
6f0da497 NI	54
	55	/* SCIF */
	56	#define CONFIG_SCIF_CONSOLE 1
	57	#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
	58	#define CONFIG_CONS_SCIF5 1
	59
	60	/* Suppress display of console information at boot */
6d0f6bcf JCPV	61	#undef CONFIG_SYS_CONSOLE_INFO_QUIET
	62	#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	63	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
6f0da497	64
6d0f6bcf JCPV	65	#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
6d0f6bcf JCPV	66	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
6f0da497 NI	67
6f0da497 NI	68	/* Enable alternate, more extensive, memory test */
6d0f6bcf	69	#undef CONFIG_SYS_ALT_MEMTEST
6f0da497	70	/* Scratch address used by the alternate memory test */
6d0f6bcf	71	#undef CONFIG_SYS_MEMTEST_SCRATCH
6f0da497 NI	72
6f0da497 NI	73	/* Enable temporary baudrate change while serial download */
6d0f6bcf	74	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
6f0da497	75
6d0f6bcf	76	#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
6f0da497	77	/* maybe more, but if so u-boot doesn't know about it... */
6d0f6bcf	78	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
6f0da497	79	/* default load address for scripts ?!? */
6d0f6bcf	80	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
6f0da497 NI	81
6f0da497 NI	82	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf	83	#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	84	/* Monitor size */
6d0f6bcf	85	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
6f0da497	86	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	87	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	88	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6f0da497 NI	89
	90	/* FLASH */
	91	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	92	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	93	#undef CONFIG_SYS_FLASH_QUIET_TEST
6f0da497	94	/* print 'E' for empty sector on flinfo */
6d0f6bcf	95	#define CONFIG_SYS_FLASH_EMPTY_INFO
6f0da497	96	/* Physical start address of Flash memory */
6d0f6bcf	97	#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	98	/* Max number of sectors on each Flash chip */
6d0f6bcf	99	#define CONFIG_SYS_MAX_FLASH_SECT 512
6f0da497 NI	100
	101	/*
	102	* IDE support
	103	*/
	104	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	105	#define CONFIG_SYS_PIO_MODE 1
	106	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	107	#define CONFIG_SYS_IDE_MAXDEVICE 1
	108	#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
	109	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	110	#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
	111	#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
	112	#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
f2a37fcd	113	#define CONFIG_IDE_SWAP_IO
6f0da497 NI	114
6f0da497 NI	115	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
6d0f6bcf JCPV	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	117	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
6f0da497 NI	118
6f0da497 NI	119	/* Timeout for Flash erase operations (in ms) */
6d0f6bcf	120	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
6f0da497	121	/* Timeout for Flash write operations (in ms) */
6d0f6bcf	122	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
6f0da497	123	/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf	124	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
6f0da497	125	/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf	126	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
6f0da497 NI	127
	128	/*
	129	* Use hardware flash sectors protection instead
	130	* of U-Boot software protection
	131	*/
6d0f6bcf JCPV	132	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	133	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
6f0da497 NI	134
6f0da497 NI	135	/* ENV setting */
5a1aceb0	136	#define CONFIG_ENV_IS_IN_FLASH
6f0da497	137	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	138	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	139	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	140	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	141	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	142	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	143	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
6f0da497 NI	144
	145	/* Board Clock */
	146	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	147	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	148	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	149	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
6f0da497 NI	150
6f0da497 NI	151	#endif /* __AP325RXA_H */