[people/ms/u-boot.git] / include / configs / ap325rxa.h

/*
 * Configuation settings for the Renesas Solutions AP-325RXA board
 *
 * Copyright (C) 2008 Renesas Solutions Corp.
 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __AP325RXA_H
#define __AP325RXA_H

#define CONFIG_CPU_SH7723	1
#define CONFIG_AP325RXA	1

#define CONFIG_CMD_SDRAM

#define CONFIG_BOOTARGS		"console=ttySC2,38400"

#define CONFIG_DISPLAY_BOARDINFO
#undef  CONFIG_SHOW_BOOT_PROGRESS

/* SMC9118 */
#define CONFIG_SMC911X 1
#define CONFIG_SMC911X_32_BIT 1
#define CONFIG_SMC911X_BASE 0xB6080000

/* MEMORY */
#define AP325RXA_SDRAM_BASE		(0x88000000)
#define AP325RXA_FLASH_BASE_1		(0xA0000000)
#define AP325RXA_FLASH_BANK_SIZE	(128 * 1024 * 1024)

#define CONFIG_SYS_TEXT_BASE	0x8FFC0000

/* undef to save memory	*/
#define CONFIG_SYS_LONGHELP
/* Monitor Command Prompt */
/* Buffer size for input from the Console */
#define CONFIG_SYS_CBSIZE		256
/* Buffer size for Console output */
#define CONFIG_SYS_PBSIZE		256
/* max args accepted for monitor commands */
#define CONFIG_SYS_MAXARGS		16
/* Buffer size for Boot Arguments passed to kernel */
#define CONFIG_SYS_BARGSIZE	512
/* List of legal baudrate settings for this board */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 38400 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE 1
#define CONFIG_SCIF_A		1 /* SH7723 has SCIF and SCIFA */
#define CONFIG_CONS_SCIF5	1

/* Suppress display of console information at boot */

#define CONFIG_SYS_MEMTEST_START	(AP325RXA_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))

/* Enable alternate, more extensive, memory test */
#undef  CONFIG_SYS_ALT_MEMTEST
/* Scratch address used by the alternate memory test */
#undef  CONFIG_SYS_MEMTEST_SCRATCH

/* Enable temporary baudrate change while serial download */
#undef  CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE	(AP325RXA_SDRAM_BASE)
/* maybe more, but if so u-boot doesn't know about it... */
#define CONFIG_SYS_SDRAM_SIZE	(128 * 1024 * 1024)
/* default load address for scripts ?!? */
#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)

/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
#define CONFIG_SYS_MONITOR_BASE	(AP325RXA_FLASH_BASE_1)
/* Monitor size */
#define CONFIG_SYS_MONITOR_LEN	(128 * 1024)
/* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)
#define CONFIG_SYS_BOOTMAPSZ	(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_FLASH_CFI_DRIVER 1
#define CONFIG_SYS_FLASH_CFI
#undef  CONFIG_SYS_FLASH_QUIET_TEST
/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_EMPTY_INFO
/* Physical start address of Flash memory */
#define CONFIG_SYS_FLASH_BASE	(AP325RXA_FLASH_BASE_1)
/* Max number of sectors on each Flash chip */
#define CONFIG_SYS_MAX_FLASH_SECT	512

/*
 * IDE support
 */
#define CONFIG_IDE_RESET	1
#define CONFIG_SYS_PIO_MODE		1
#define CONFIG_SYS_IDE_MAXBUS		1	/* IDE bus */
#define CONFIG_SYS_IDE_MAXDEVICE	1
#define CONFIG_SYS_ATA_BASE_ADDR	0xB4180000
#define CONFIG_SYS_ATA_STRIDE		2	/* 1bit shift */
#define CONFIG_SYS_ATA_DATA_OFFSET	0x200	/* data reg offset */
#define CONFIG_SYS_ATA_REG_OFFSET	0x200	/* reg offset */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x210	/* alternate register offset */
#define CONFIG_IDE_SWAP_IO

/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}

/* Timeout for Flash erase operations (in ms) */
#define CONFIG_SYS_FLASH_ERASE_TOUT	(3 * 1000)
/* Timeout for Flash write operations (in ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	(3 * 1000)
/* Timeout for Flash set sector lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_LOCK_TOUT	(3 * 1000)
/* Timeout for Flash clear lock bit operations (in ms) */
#define CONFIG_SYS_FLASH_UNLOCK_TOUT	(3 * 1000)

/*
 * Use hardware flash sectors protection instead
 * of U-Boot software protection
 */
#undef  CONFIG_SYS_FLASH_PROTECTION
#undef  CONFIG_SYS_DIRECT_FLASH_TFTP

/* ENV setting */
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SECT_SIZE	(128 * 1024)
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
#define CONFIG_ENV_OFFSET		(CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	33333333
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV		(4)	/* 4 (default), 16, 64, 256 or 1024 */

#endif	/* __AP325RXA_H */
Commit	Line	Data
6f0da497 NI	1	/*
	2	* Configuation settings for the Renesas Solutions AP-325RXA board
	3	*
	4	* Copyright (C) 2008 Renesas Solutions Corp.
	5	* Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
6f0da497 NI	8	*/
	9
	10	#ifndef __AP325RXA_H
	11	#define __AP325RXA_H
	12
6f0da497 NI	13	#define CONFIG_CPU_SH7723 1
	14	#define CONFIG_AP325RXA 1
	15
6f0da497	16	#define CONFIG_CMD_SDRAM
6f0da497	17
6f0da497 NI	18	#define CONFIG_BOOTARGS "console=ttySC2,38400"
6f0da497 NI	19
18a40e84	20	#define CONFIG_DISPLAY_BOARDINFO
6f0da497 NI	21	#undef CONFIG_SHOW_BOOT_PROGRESS
	22
	23	/* SMC9118 */
736fead8 BW	24	#define CONFIG_SMC911X 1
	25	#define CONFIG_SMC911X_32_BIT 1
	26	#define CONFIG_SMC911X_BASE 0xB6080000
6f0da497 NI	27
	28	/* MEMORY */
	29	#define AP325RXA_SDRAM_BASE (0x88000000)
	30	#define AP325RXA_FLASH_BASE_1 (0xA0000000)
	31	#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
	32
db68b703 NI	33	#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
db68b703 NI	34
6f0da497	35	/* undef to save memory */
6d0f6bcf	36	#define CONFIG_SYS_LONGHELP
6f0da497	37	/* Monitor Command Prompt */
6f0da497	38	/* Buffer size for input from the Console */
6d0f6bcf	39	#define CONFIG_SYS_CBSIZE 256
6f0da497	40	/* Buffer size for Console output */
6d0f6bcf	41	#define CONFIG_SYS_PBSIZE 256
6f0da497	42	/* max args accepted for monitor commands */
6d0f6bcf	43	#define CONFIG_SYS_MAXARGS 16
6f0da497	44	/* Buffer size for Boot Arguments passed to kernel */
6d0f6bcf	45	#define CONFIG_SYS_BARGSIZE 512
6f0da497	46	/* List of legal baudrate settings for this board */
6d0f6bcf	47	#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
6f0da497 NI	48
	49	/* SCIF */
	50	#define CONFIG_SCIF_CONSOLE 1
	51	#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
	52	#define CONFIG_CONS_SCIF5 1
	53
	54	/* Suppress display of console information at boot */
6f0da497	55
6d0f6bcf JCPV	56	#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
6d0f6bcf JCPV	57	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
6f0da497 NI	58
6f0da497 NI	59	/* Enable alternate, more extensive, memory test */
6d0f6bcf	60	#undef CONFIG_SYS_ALT_MEMTEST
6f0da497	61	/* Scratch address used by the alternate memory test */
6d0f6bcf	62	#undef CONFIG_SYS_MEMTEST_SCRATCH
6f0da497 NI	63
6f0da497 NI	64	/* Enable temporary baudrate change while serial download */
6d0f6bcf	65	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
6f0da497	66
6d0f6bcf	67	#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
6f0da497	68	/* maybe more, but if so u-boot doesn't know about it... */
6d0f6bcf	69	#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
6f0da497	70	/* default load address for scripts ?!? */
6d0f6bcf	71	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
6f0da497 NI	72
6f0da497 NI	73	/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
6d0f6bcf	74	#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	75	/* Monitor size */
6d0f6bcf	76	#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
6f0da497	77	/* Size of DRAM reserved for malloc() use */
6d0f6bcf	78	#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
6d0f6bcf	79	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
6f0da497 NI	80
	81	/* FLASH */
	82	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	83	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	84	#undef CONFIG_SYS_FLASH_QUIET_TEST
6f0da497	85	/* print 'E' for empty sector on flinfo */
6d0f6bcf	86	#define CONFIG_SYS_FLASH_EMPTY_INFO
6f0da497	87	/* Physical start address of Flash memory */
6d0f6bcf	88	#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
6f0da497	89	/* Max number of sectors on each Flash chip */
6d0f6bcf	90	#define CONFIG_SYS_MAX_FLASH_SECT 512
6f0da497 NI	91
	92	/*
	93	* IDE support
	94	*/
	95	#define CONFIG_IDE_RESET 1
6d0f6bcf JCPV	96	#define CONFIG_SYS_PIO_MODE 1
	97	#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
	98	#define CONFIG_SYS_IDE_MAXDEVICE 1
	99	#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
	100	#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
	101	#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
	102	#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
	103	#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
f2a37fcd	104	#define CONFIG_IDE_SWAP_IO
6f0da497 NI	105
6f0da497 NI	106	/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
6d0f6bcf JCPV	107	#define CONFIG_SYS_MAX_FLASH_BANKS 1
6d0f6bcf JCPV	108	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
6f0da497 NI	109
6f0da497 NI	110	/* Timeout for Flash erase operations (in ms) */
6d0f6bcf	111	#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
6f0da497	112	/* Timeout for Flash write operations (in ms) */
6d0f6bcf	113	#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
6f0da497	114	/* Timeout for Flash set sector lock bit operations (in ms) */
6d0f6bcf	115	#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
6f0da497	116	/* Timeout for Flash clear lock bit operations (in ms) */
6d0f6bcf	117	#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
6f0da497 NI	118
	119	/*
	120	* Use hardware flash sectors protection instead
	121	* of U-Boot software protection
	122	*/
6d0f6bcf JCPV	123	#undef CONFIG_SYS_FLASH_PROTECTION
6d0f6bcf JCPV	124	#undef CONFIG_SYS_DIRECT_FLASH_TFTP
6f0da497 NI	125
6f0da497 NI	126	/* ENV setting */
6f0da497	127	#define CONFIG_ENV_OVERWRITE 1
0e8d1586 JCPV	128	#define CONFIG_ENV_SECT_SIZE (128 * 1024)
0e8d1586 JCPV	129	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
6d0f6bcf JCPV	130	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
	131	/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
	132	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
0e8d1586	133	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
6f0da497 NI	134
	135	/* Board Clock */
	136	#define CONFIG_SYS_CLK_FREQ 33333333
684a501e NI	137	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	138	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
be45c632	139	#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
6f0da497 NI	140
6f0da497 NI	141	#endif /* __AP325RXA_H */