projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 52568c36 WD |
1 | /* |
| 2 | * (C) Copyright 2009 Wolfgang Denk <wd@denx.de> | |
| 3 | * (C) Copyright 2009, DAVE Srl <www.dave.eu> | |
| 4 | * | |
| 3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
| 52568c36 WD |
6 | */ |
| 7 | ||
| 8 | /* | |
| 9 | * Aria board configuration file | |
| 10 | */ | |
| 11 | ||
| 12 | #ifndef __CONFIG_H | |
| 13 | #define __CONFIG_H | |
| 14 | ||
| 15 | #define CONFIG_ARIA 1 | |
| 32ff89dc | 16 | |
| 52568c36 WD |
17 | /* |
| 18 | * Memory map for the ARIA board: | |
| 19 | * | |
| 20 | * 0x0000_0000-0x0FFF_FFFF DDR RAM (256 MB) | |
| 21 | * 0x3000_0000-0x3001_FFFF On Chip SRAM (128 KB) | |
| 22 | * 0x3010_0000-0x3011_FFFF On Board SRAM (128 KB) - CS6 | |
| 23 | * 0x3020_0000-0x3021_FFFF FPGA (128 KB) - CS2 | |
| 24 | * 0x8000_0000-0x803F_FFFF IMMR (4 MB) | |
| 25 | * 0x8400_0000-0x82FF_FFFF PCI I/O space (16 MB) | |
| 26 | * 0xA000_0000-0xAFFF_FFFF PCI memory space (256 MB) | |
| 27 | * 0xB000_0000-0xBFFF_FFFF PCI memory mapped I/O space (256 MB) | |
| 28 | * 0xFC00_0000-0xFFFF_FFFF NOR Boot FLASH (64 MB) | |
| 29 | */ | |
| 30 | ||
| 31 | /* | |
| 32 | * High Level Configuration Options | |
| 33 | */ | |
| 34 | #define CONFIG_E300 1 /* E300 Family */ | |
| 52568c36 | 35 | #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ |
| 52568c36 | 36 | |
| 2ae18241 WD |
37 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
| 38 | ||
| 52568c36 | 39 | /* video */ |
| 52568c36 | 40 | |
| 52568c36 WD |
41 | /* CONFIG_PCI is defined at config time */ |
| 42 | ||
| 43 | #define CONFIG_SYS_MPC512X_CLKIN 33000000 /* in Hz */ | |
| 44 | ||
| 52568c36 WD |
45 | #define CONFIG_MISC_INIT_R |
| 46 | ||
| 47 | #define CONFIG_SYS_IMMR 0x80000000 | |
| 48 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_IMMR+0x2100) | |
| 49 | ||
| 50 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
| 51 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| 52 | ||
| 53 | /* | |
| 54 | * DDR Setup - manually set all parameters as there's no SPD etc. | |
| 55 | */ | |
| 56 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ | |
| 57 | #define CONFIG_SYS_DDR_BASE 0x00000000 | |
| 58 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
| b9947bbb | 59 | #define CONFIG_SYS_MAX_RAM_SIZE 0x20000000 |
| 52568c36 | 60 | |
| 5d937e8b AG |
61 | #define CONFIG_SYS_IOCTRL_MUX_DDR 0x00000036 |
| 62 | ||
| 52568c36 WD |
63 | /* DDR Controller Configuration |
| 64 | * | |
| 65 | * SYS_CFG: | |
| 66 | * [31:31] MDDRC Soft Reset: Diabled | |
| 67 | * [30:30] DRAM CKE pin: Enabled | |
| 68 | * [29:29] DRAM CLK: Enabled | |
| 69 | * [28:28] Command Mode: Enabled (For initialization only) | |
| 70 | * [27:25] DRAM Row Select: dram_row[15:0] = magenta_address[25:10] | |
| 71 | * [24:21] DRAM Bank Select: dram_bank[1:0] = magenta_address[11:10] | |
| 72 | * [20:19] Read Test: DON'T USE | |
| 73 | * [18:18] Self Refresh: Enabled | |
| 74 | * [17:17] 16bit Mode: Disabled | |
| 75 | * [16:13] Ready Delay: 2 | |
| 76 | * [12:12] Half DQS Delay: Disabled | |
| 77 | * [11:11] Quarter DQS Delay: Disabled | |
| 78 | * [10:08] Write Delay: 2 | |
| 79 | * [07:07] Early ODT: Disabled | |
| 80 | * [06:06] On DIE Termination: Disabled | |
| 81 | * [05:05] FIFO Overflow Clear: DON'T USE here | |
| 82 | * [04:04] FIFO Underflow Clear: DON'T USE here | |
| 83 | * [03:03] FIFO Overflow Pending: DON'T USE here | |
| 84 | * [02:02] FIFO Underlfow Pending: DON'T USE here | |
| 85 | * [01:01] FIFO Overlfow Enabled: Enabled | |
| 86 | * [00:00] FIFO Underflow Enabled: Enabled | |
| 87 | * TIME_CFG0 | |
| 88 | * [31:16] DRAM Refresh Time: 0 CSB clocks | |
| 89 | * [15:8] DRAM Command Time: 0 CSB clocks | |
| 90 | * [07:00] DRAM Precharge Time: 0 CSB clocks | |
| 91 | * TIME_CFG1 | |
| 92 | * [31:26] DRAM tRFC: | |
| 93 | * [25:21] DRAM tWR1: | |
| 94 | * [20:17] DRAM tWRT1: | |
| 95 | * [16:11] DRAM tDRR: | |
| 96 | * [10:05] DRAM tRC: | |
| 97 | * [04:00] DRAM tRAS: | |
| 98 | * TIME_CFG2 | |
| 99 | * [31:28] DRAM tRCD: | |
| 100 | * [27:23] DRAM tFAW: | |
| 101 | * [22:19] DRAM tRTW1: | |
| 102 | * [18:15] DRAM tCCD: | |
| 103 | * [14:10] DRAM tRTP: | |
| 104 | * [09:05] DRAM tRP: | |
| 105 | * [04:00] DRAM tRPA | |
| 106 | */ | |
| 25671c86 WD |
107 | #define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \ |
| 108 | (1 << 30) | /* CKE */ \ | |
| 109 | (1 << 29) | /* CLK_ON */ \ | |
| 054197ba | 110 | (0 << 28) | /* CMD_MODE */ \ |
| 25671c86 WD |
111 | (4 << 25) | /* DRAM_ROW_SELECT */ \ |
| 112 | (3 << 21) | /* DRAM_BANK_SELECT */ \ | |
| 113 | (0 << 18) | /* SELF_REF_EN */ \ | |
| 114 | (0 << 17) | /* 16BIT_MODE */ \ | |
| 115 | (2 << 13) | /* RDLY */ \ | |
| 116 | (0 << 12) | /* HALF_DQS_DLY */ \ | |
| 117 | (1 << 11) | /* QUART_DQS_DLY */ \ | |
| 118 | (2 << 8) | /* WDLY */ \ | |
| 119 | (0 << 7) | /* EARLY_ODT */ \ | |
| 120 | (1 << 6) | /* ON_DIE_TERMINATE */ \ | |
| 121 | (0 << 5) | /* FIFO_OV_CLEAR */ \ | |
| 122 | (0 << 4) | /* FIFO_UV_CLEAR */ \ | |
| 123 | (0 << 1) | /* FIFO_OV_EN */ \ | |
| 124 | (0 << 0) /* FIFO_UV_EN */ \ | |
| 125 | ) | |
| 126 | ||
| 054197ba | 127 | #define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E |
| 25671c86 WD |
128 | #define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189 |
| 129 | #define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863 | |
| 52568c36 | 130 | |
| 054197ba MS |
131 | #define CONFIG_SYS_DDRCMD_NOP 0x01380000 |
| 132 | #define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400 | |
| 25671c86 WD |
133 | #define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \ |
| 134 | (0 << 22) | /* DRAM_CS */ \ | |
| 135 | (0 << 21) | /* DRAM_RAS */ \ | |
| 136 | (0 << 20) | /* DRAM_CAS */ \ | |
| 137 | (0 << 19) | /* DRAM_WEB */ \ | |
| 138 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
| 139 | (0 << 15) | /* */ \ | |
| 140 | (0 << 12) | /* A12->out */ \ | |
| 141 | (0 << 11) | /* A11->RDQS */ \ | |
| 142 | (0 << 10) | /* A10->DQS# */ \ | |
| 143 | (0 << 7) | /* OCD program */ \ | |
| 144 | (0 << 6) | /* Rtt1 */ \ | |
| 145 | (0 << 3) | /* posted CAS# */ \ | |
| 146 | (0 << 2) | /* Rtt0 */ \ | |
| 147 | (1 << 1) | /* ODS */ \ | |
| 148 | (0 << 0) /* DLL */ \ | |
| 149 | ) | |
| 150 | #define CONFIG_SYS_MICRON_EMR2 0x01020000 | |
| 151 | #define CONFIG_SYS_MICRON_EMR3 0x01030000 | |
| 054197ba | 152 | #define CONFIG_SYS_DDRCMD_RFSH 0x01080000 |
| 52568c36 | 153 | #define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432 |
| 25671c86 WD |
154 | #define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \ |
| 155 | (0 << 22) | /* DRAM_CS */ \ | |
| 156 | (0 << 21) | /* DRAM_RAS */ \ | |
| 157 | (0 << 20) | /* DRAM_CAS */ \ | |
| 158 | (0 << 19) | /* DRAM_WEB */ \ | |
| 159 | (1 << 16) | /* DRAM_BS[2:0] */ \ | |
| 160 | (0 << 15) | /* */ \ | |
| 161 | (0 << 12) | /* A12->out */ \ | |
| 162 | (0 << 11) | /* A11->RDQS */ \ | |
| 163 | (1 << 10) | /* A10->DQS# */ \ | |
| 164 | (7 << 7) | /* OCD program */ \ | |
| 165 | (0 << 6) | /* Rtt1 */ \ | |
| 166 | (0 << 3) | /* posted CAS# */ \ | |
| 167 | (1 << 2) | /* Rtt0 */ \ | |
| 168 | (0 << 1) | /* ODS (Output Drive Strength) */ \ | |
| 169 | (0 << 0) /* DLL */ \ | |
| 170 | ) | |
| 171 | ||
| 172 | /* | |
| 173 | * Backward compatible definitions, | |
| a47a12be | 174 | * so we do not have to change arch/powerpc/cpu/mpc512x/fixed_sdram.c |
| 25671c86 | 175 | */ |
| 054197ba MS |
176 | #define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2) |
| 177 | #define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3) | |
| 178 | #define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR) | |
| 179 | #define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD) | |
| 52568c36 WD |
180 | |
| 181 | /* DDR Priority Manager Configuration */ | |
| 182 | #define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777 | |
| 183 | #define CONFIG_SYS_MDDRCGRP_PM_CFG2 0x00000000 | |
| 184 | #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG 0x00000001 | |
| 185 | #define CONFIG_SYS_MDDRCGRP_LUT0_MU 0xFFEEDDCC | |
| 186 | #define CONFIG_SYS_MDDRCGRP_LUT0_ML 0xBBAAAAAA | |
| 187 | #define CONFIG_SYS_MDDRCGRP_LUT1_MU 0x66666666 | |
| 188 | #define CONFIG_SYS_MDDRCGRP_LUT1_ML 0x55555555 | |
| 189 | #define CONFIG_SYS_MDDRCGRP_LUT2_MU 0x44444444 | |
| 190 | #define CONFIG_SYS_MDDRCGRP_LUT2_ML 0x44444444 | |
| 191 | #define CONFIG_SYS_MDDRCGRP_LUT3_MU 0x55555555 | |
| 192 | #define CONFIG_SYS_MDDRCGRP_LUT3_ML 0x55555558 | |
| 193 | #define CONFIG_SYS_MDDRCGRP_LUT4_MU 0x11111111 | |
| 194 | #define CONFIG_SYS_MDDRCGRP_LUT4_ML 0x11111122 | |
| 195 | #define CONFIG_SYS_MDDRCGRP_LUT0_AU 0xaaaaaaaa | |
| 196 | #define CONFIG_SYS_MDDRCGRP_LUT0_AL 0xaaaaaaaa | |
| 197 | #define CONFIG_SYS_MDDRCGRP_LUT1_AU 0x66666666 | |
| 198 | #define CONFIG_SYS_MDDRCGRP_LUT1_AL 0x66666666 | |
| 199 | #define CONFIG_SYS_MDDRCGRP_LUT2_AU 0x11111111 | |
| 200 | #define CONFIG_SYS_MDDRCGRP_LUT2_AL 0x11111111 | |
| 201 | #define CONFIG_SYS_MDDRCGRP_LUT3_AU 0x11111111 | |
| 202 | #define CONFIG_SYS_MDDRCGRP_LUT3_AL 0x11111111 | |
| 203 | #define CONFIG_SYS_MDDRCGRP_LUT4_AU 0x11111111 | |
| 204 | #define CONFIG_SYS_MDDRCGRP_LUT4_AL 0x11111111 | |
| 205 | ||
| 206 | /* | |
| 207 | * NOR FLASH on the Local Bus | |
| 208 | */ | |
| 209 | #define CONFIG_SYS_FLASH_CFI /* use the CFI code */ | |
| 210 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 211 | #define CONFIG_SYS_FLASH_BASE 0xF8000000 /* start of FLASH */ | |
| 212 | #define CONFIG_SYS_FLASH_SIZE 0x08000000 /* max flash size */ | |
| 213 | ||
| 214 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 215 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 216 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} | |
| 217 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* max sectors */ | |
| 218 | ||
| 219 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
| 220 | ||
| a6d6d46a WD |
221 | /* |
| 222 | * NAND FLASH support | |
| 223 | * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only) | |
| 224 | */ | |
| 1f1f82f3 WD |
225 | #define CONFIG_CMD_NAND /* enable NAND support */ |
| 226 | #define CONFIG_JFFS2_NAND /* with JFFS2 on it */ | |
| a6d6d46a WD |
227 | #define CONFIG_NAND_MPC5121_NFC |
| 228 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
| a6d6d46a | 229 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| a6d6d46a | 230 | |
| a6d6d46a WD |
231 | /* |
| 232 | * Configuration parameters for MPC5121 NAND driver | |
| 233 | */ | |
| 234 | #define CONFIG_FSL_NFC_WIDTH 1 | |
| 235 | #define CONFIG_FSL_NFC_WRITE_SIZE 2048 | |
| 236 | #define CONFIG_FSL_NFC_SPARE_SIZE 64 | |
| 237 | #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
| 238 | ||
| 52568c36 WD |
239 | #define CONFIG_SYS_SRAM_BASE 0x30000000 |
| 240 | #define CONFIG_SYS_SRAM_SIZE 0x00020000 /* 128 KB */ | |
| 241 | ||
| 25671c86 WD |
242 | /* Make two SRAM regions contiguous */ |
| 243 | #define CONFIG_SYS_ARIA_SRAM_BASE (CONFIG_SYS_SRAM_BASE + \ | |
| 244 | CONFIG_SYS_SRAM_SIZE) | |
| 245 | #define CONFIG_SYS_ARIA_SRAM_SIZE 0x00100000 /* reserve 1MB-window */ | |
| 676c6691 AG |
246 | #define CONFIG_SYS_CS6_START CONFIG_SYS_ARIA_SRAM_BASE |
| 247 | #define CONFIG_SYS_CS6_SIZE CONFIG_SYS_ARIA_SRAM_SIZE | |
| 52568c36 WD |
248 | |
| 249 | #define CONFIG_SYS_ARIA_FPGA_BASE (CONFIG_SYS_ARIA_SRAM_BASE + \ | |
| 250 | CONFIG_SYS_ARIA_SRAM_SIZE) | |
| 251 | #define CONFIG_SYS_ARIA_FPGA_SIZE 0x20000 /* 128 KB */ | |
| 252 | ||
| 676c6691 AG |
253 | #define CONFIG_SYS_CS2_START CONFIG_SYS_ARIA_FPGA_BASE |
| 254 | #define CONFIG_SYS_CS2_SIZE CONFIG_SYS_ARIA_FPGA_SIZE | |
| 255 | ||
| 52568c36 WD |
256 | #define CONFIG_SYS_CS0_CFG 0x05059150 |
| 257 | #define CONFIG_SYS_CS2_CFG ( (5 << 24) | \ | |
| 258 | (5 << 16) | \ | |
| 259 | (1 << 15) | \ | |
| 260 | (0 << 14) | \ | |
| 261 | (0 << 13) | \ | |
| 262 | (1 << 12) | \ | |
| 263 | (0 << 10) | \ | |
| 264 | (3 << 8) | /* 32 bit */ \ | |
| 265 | (0 << 7) | \ | |
| 266 | (1 << 6) | \ | |
| 267 | (1 << 4) | \ | |
| 268 | (0 << 3) | \ | |
| 269 | (0 << 2) | \ | |
| 270 | (0 << 1) | \ | |
| 271 | (0 << 0) \ | |
| 272 | ) | |
| 273 | #define CONFIG_SYS_CS6_CFG 0x05059150 | |
| 274 | ||
| 275 | /* Use alternative CS timing for CS0 and CS2 */ | |
| 276 | #define CONFIG_SYS_CS_ALETIMING 0x00000005 | |
| 277 | ||
| 278 | /* Use SRAM for initial stack */ | |
| 279 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SRAM_BASE | |
| 553f0982 | 280 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_SRAM_SIZE |
| 52568c36 | 281 | |
| 553f0982 | 282 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \ |
| 25ddd1fb | 283 | GENERATED_GBL_DATA_SIZE) |
| 52568c36 WD |
284 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 285 | ||
| 14d0a02a | 286 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
| a6d6d46a | 287 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) |
| 52568c36 WD |
288 | |
| 289 | #ifdef CONFIG_FSL_DIU_FB | |
| 290 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) | |
| 291 | #else | |
| 292 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
| 293 | #endif | |
| 294 | ||
| 295 | /* FPGA */ | |
| 296 | #define CONFIG_ARIA_FPGA 1 | |
| 297 | ||
| 298 | /* | |
| 299 | * Serial Port | |
| 300 | */ | |
| 301 | #define CONFIG_CONS_INDEX 1 | |
| 52568c36 WD |
302 | |
| 303 | /* | |
| 304 | * Serial console configuration | |
| 305 | */ | |
| 306 | #define CONFIG_PSC_CONSOLE 3 /* console on PSC3 */ | |
| bfb31279 | 307 | #define CONFIG_SYS_PSC3 |
| 52568c36 WD |
308 | #if CONFIG_PSC_CONSOLE != 3 |
| 309 | #error CONFIG_PSC_CONSOLE must be 3 | |
| 310 | #endif | |
| 311 | ||
| 52568c36 WD |
312 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 313 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 314 | ||
| 315 | #define CONSOLE_FIFO_TX_SIZE FIFOC_PSC3_TX_SIZE | |
| 316 | #define CONSOLE_FIFO_TX_ADDR FIFOC_PSC3_TX_ADDR | |
| 317 | #define CONSOLE_FIFO_RX_SIZE FIFOC_PSC3_RX_SIZE | |
| 318 | #define CONSOLE_FIFO_RX_ADDR FIFOC_PSC3_RX_ADDR | |
| 319 | ||
| 320 | #define CONFIG_CMDLINE_EDITING 1 /* command line history */ | |
| 52568c36 WD |
321 | |
| 322 | /* | |
| 323 | * PCI | |
| 324 | */ | |
| 325 | #ifdef CONFIG_PCI | |
| 842033e6 | 326 | #define CONFIG_PCI_INDIRECT_BRIDGE |
| 52568c36 WD |
327 | |
| 328 | #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000 | |
| 329 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE | |
| 330 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
| 331 | #define CONFIG_SYS_PCI_MMIO_BASE (CONFIG_SYS_PCI_MEM_BASE + \ | |
| 332 | CONFIG_SYS_PCI_MEM_SIZE) | |
| 333 | #define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE | |
| 334 | #define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
| 335 | #define CONFIG_SYS_PCI_IO_BASE 0x00000000 | |
| 336 | #define CONFIG_SYS_PCI_IO_PHYS 0x84000000 | |
| 337 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 /* 16M */ | |
| 338 | ||
| 52568c36 WD |
339 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| 340 | ||
| 341 | #endif | |
| 342 | ||
| 343 | /* I2C */ | |
| 344 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 52568c36 | 345 | #define CONFIG_I2C_MULTI_BUS |
| 52568c36 WD |
346 | |
| 347 | /* I2C speed and slave address */ | |
| 348 | #define CONFIG_SYS_I2C_SPEED 100000 | |
| 349 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 350 | #if 0 | |
| 351 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
| 352 | #endif | |
| 353 | ||
| 354 | /* | |
| 355 | * IIM - IC Identification Module | |
| 356 | */ | |
| 83306927 | 357 | #undef CONFIG_FSL_IIM |
| 52568c36 WD |
358 | |
| 359 | /* | |
| 360 | * EEPROM configuration for Atmel AT24C32A-10TQ-2.7: | |
| 361 | * 16-bit addresses, 10ms write delay, 32-Byte Page Write Mode | |
| 362 | */ | |
| 363 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
| 364 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 | |
| 365 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
| 366 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 | |
| 367 | ||
| 368 | /* | |
| 369 | * Ethernet configuration | |
| 370 | */ | |
| 371 | #define CONFIG_MPC512x_FEC 1 | |
| 52568c36 WD |
372 | #define CONFIG_PHY_ADDR 0x17 |
| 373 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 374 | #define CONFIG_FEC_AN_TIMEOUT 1 | |
| 375 | #define CONFIG_HAS_ETH0 | |
| 376 | ||
| 377 | /* | |
| 378 | * Environment | |
| 379 | */ | |
| 380 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
| 381 | /* This has to be a multiple of the flash sector size */ | |
| 382 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ | |
| 383 | CONFIG_SYS_MONITOR_LEN) | |
| 384 | #define CONFIG_ENV_SIZE 0x2000 | |
| 385 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (256K) */ | |
| 386 | ||
| 387 | /* Address and size of Redundant Environment Sector */ | |
| 388 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + \ | |
| 389 | CONFIG_ENV_SECT_SIZE) | |
| 390 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
| 391 | ||
| 392 | #define CONFIG_LOADS_ECHO 1 | |
| 393 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 | |
| 394 | ||
| 52568c36 WD |
395 | #define CONFIG_CMD_EEPROM |
| 396 | #undef CONFIG_CMD_FUSE | |
| 52568c36 | 397 | #undef CONFIG_CMD_IDE |
| 1f1f82f3 | 398 | #define CONFIG_CMD_JFFS2 |
| 52568c36 WD |
399 | #define CONFIG_CMD_REGINFO |
| 400 | ||
| 401 | #if defined(CONFIG_PCI) | |
| 402 | #define CONFIG_CMD_PCI | |
| 403 | #endif | |
| 404 | ||
| 1f1f82f3 WD |
405 | /* |
| 406 | * Dynamic MTD partition support | |
| 407 | */ | |
| 408 | #define CONFIG_CMD_MTDPARTS | |
| 409 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ | |
| 410 | #define CONFIG_FLASH_CFI_MTD | |
| 411 | #define MTDIDS_DEFAULT "nor0=f8000000.flash,nand0=mpc5121.nand" | |
| 412 | ||
| 413 | /* | |
| 414 | * NOR flash layout: | |
| 415 | * | |
| 416 | * F8000000 - FEAFFFFF 107 MiB User Data | |
| 417 | * FEB00000 - FFAFFFFF 16 MiB Root File System | |
| 418 | * FFB00000 - FFFEFFFF 4 MiB Linux Kernel | |
| 419 | * FFF00000 - FFFBFFFF 768 KiB U-Boot (up to 512 KiB) and 2 x * env | |
| 420 | * FFFC0000 - FFFFFFFF 256 KiB Device Tree | |
| 421 | * | |
| 422 | * NAND flash layout: one big partition | |
| 423 | */ | |
| 424 | #define MTDPARTS_DEFAULT "mtdparts=f8000000.flash:107m(user)," \ | |
| 425 | "16m(rootfs)," \ | |
| 426 | "4m(kernel)," \ | |
| 427 | "768k(u-boot)," \ | |
| 428 | "256k(dtb);" \ | |
| 429 | "mpc5121.nand:-(data)" | |
| 430 | ||
| 52568c36 WD |
431 | /* |
| 432 | * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock. | |
| 433 | * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE | |
| 434 | * is set to 0xFFFF, watchdog timeouts after about 64s. For details | |
| 435 | * refer to chapter 36 of the MPC5121e Reference Manual. | |
| 436 | */ | |
| 437 | /* #define CONFIG_WATCHDOG */ /* enable watchdog */ | |
| 438 | #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF | |
| 439 | ||
| 440 | /* | |
| 441 | * Miscellaneous configurable options | |
| 442 | */ | |
| 443 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
| 444 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
| 52568c36 WD |
445 | |
| 446 | #ifdef CONFIG_CMD_KGDB | |
| 447 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 448 | #else | |
| 449 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 450 | #endif | |
| 451 | ||
| 452 | /* Print Buffer Size */ | |
| 453 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
| 454 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
| 455 | /* max number of command args */ | |
| 456 | #define CONFIG_SYS_MAXARGS 32 | |
| 457 | /* Boot Argument Buffer Size */ | |
| 458 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
| 459 | ||
| 52568c36 WD |
460 | /* |
| 461 | * For booting Linux, the board info and command line data | |
| 9f530d59 | 462 | * have to be in the first 256 MB of memory, since this is |
| 52568c36 WD |
463 | * the maximum mapped by the Linux kernel during initialization. |
| 464 | */ | |
| 9f530d59 | 465 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) |
| 52568c36 WD |
466 | |
| 467 | /* Cache Configuration */ | |
| 468 | #define CONFIG_SYS_DCACHE_SIZE 32768 | |
| 469 | #define CONFIG_SYS_CACHELINE_SIZE 32 | |
| 470 | #ifdef CONFIG_CMD_KGDB | |
| 471 | #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of 32 */ | |
| 472 | #endif | |
| 473 | ||
| 474 | #define CONFIG_SYS_HID0_INIT 0x000000000 | |
| 475 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
| 476 | HID0_ICE) | |
| 477 | #define CONFIG_SYS_HID2 HID2_HBE | |
| 478 | ||
| 479 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ | |
| 480 | ||
| 52568c36 WD |
481 | #ifdef CONFIG_CMD_KGDB |
| 482 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| 52568c36 WD |
483 | #endif |
| 484 | ||
| 485 | /* | |
| 486 | * Environment Configuration | |
| 487 | */ | |
| 488 | #define CONFIG_ENV_OVERWRITE | |
| 489 | #define CONFIG_TIMESTAMP | |
| 490 | ||
| 491 | #define CONFIG_HOSTNAME aria | |
| b3f44c21 | 492 | #define CONFIG_BOOTFILE "aria/uImage" |
| 8b3637c6 | 493 | #define CONFIG_ROOTPATH "/opt/eldk/ppc_6xx" |
| 52568c36 WD |
494 | |
| 495 | #define CONFIG_LOADADDR 400000 /* default load addr */ | |
| 496 | ||
| 52568c36 WD |
497 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| 498 | ||
| 52568c36 WD |
499 | #define CONFIG_PREBOOT "echo;" \ |
| 500 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
| 501 | "echo" | |
| 502 | ||
| 503 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 504 | "u-boot_addr_r=200000\0" \ | |
| 505 | "kernel_addr_r=600000\0" \ | |
| 506 | "fdt_addr_r=880000\0" \ | |
| 507 | "ramdisk_addr_r=900000\0" \ | |
| 508 | "u-boot_addr=FFF00000\0" \ | |
| 1f1f82f3 WD |
509 | "kernel_addr=FFB00000\0" \ |
| 510 | "fdt_addr=FFFC0000\0" \ | |
| 511 | "ramdisk_addr=FEB00000\0" \ | |
| 52568c36 WD |
512 | "ramdiskfile=aria/uRamdisk\0" \ |
| 513 | "u-boot=aria/u-boot.bin\0" \ | |
| 514 | "fdtfile=aria/aria.dtb\0" \ | |
| 515 | "netdev=eth0\0" \ | |
| 516 | "consdev=ttyPSC0\0" \ | |
| 517 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
| 518 | "nfsroot=${serverip}:${rootpath}\0" \ | |
| 519 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
| 520 | "addip=setenv bootargs ${bootargs} " \ | |
| 521 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
| 522 | ":${hostname}:${netdev}:off panic=1\0" \ | |
| 523 | "addtty=setenv bootargs ${bootargs} " \ | |
| 524 | "console=${consdev},${baudrate}\0" \ | |
| 525 | "flash_nfs=run nfsargs addip addtty;" \ | |
| 526 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
| 527 | "flash_self=run ramargs addip addtty;" \ | |
| 528 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ | |
| 529 | "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 530 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
| 531 | "run nfsargs addip addtty;" \ | |
| 532 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
| 533 | "net_self=tftp ${kernel_addr_r} ${bootfile};" \ | |
| 534 | "tftp ${ramdisk_addr_r} ${ramdiskfile};" \ | |
| 535 | "tftp ${fdt_addr_r} ${fdtfile};" \ | |
| 536 | "run ramargs addip addtty;" \ | |
| 537 | "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\ | |
| 538 | "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ | |
| 539 | "update=protect off ${u-boot_addr} +${filesize};" \ | |
| 540 | "era ${u-boot_addr} +${filesize};" \ | |
| 541 | "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0" \ | |
| 542 | "upd=run load update\0" \ | |
| 543 | "" | |
| 544 | ||
| 545 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
| 546 | ||
| 52568c36 WD |
547 | #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES 1 |
| 548 | ||
| 549 | #define OF_CPU "PowerPC,5121@0" | |
| 550 | #define OF_SOC_COMPAT "fsl,mpc5121-immr" | |
| 551 | #define OF_TBCLK (bd->bi_busfreq / 4) | |
| 552 | #define OF_STDOUT_PATH "/soc@80000000/serial@11300" | |
| 553 | ||
| 554 | /*----------------------------------------------------------------------- | |
| 555 | * IDE/ATA stuff | |
| 556 | *----------------------------------------------------------------------- | |
| 557 | */ | |
| 558 | ||
| 559 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ | |
| 560 | #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ | |
| 561 | #undef CONFIG_IDE_LED /* LED for IDE not supported */ | |
| 562 | ||
| 563 | #define CONFIG_IDE_RESET /* reset for IDE supported */ | |
| 564 | #define CONFIG_IDE_PREINIT | |
| 565 | ||
| 566 | #define CONFIG_SYS_IDE_MAXBUS 1 /* 1 IDE bus */ | |
| 567 | #define CONFIG_SYS_IDE_MAXDEVICE 2 /* 1 drive per IDE bus */ | |
| 568 | ||
| 569 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
| 570 | #define CONFIG_SYS_ATA_BASE_ADDR get_pata_base() | |
| 571 | ||
| 572 | /* Offset for data I/O RefMan MPC5121EE Table 28-10 */ | |
| 573 | #define CONFIG_SYS_ATA_DATA_OFFSET (0x00A0) | |
| 574 | ||
| 575 | /* Offset for normal register accesses */ | |
| 576 | #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) | |
| 577 | ||
| 578 | /* Offset for alternate registers RefMan MPC5121EE Table 28-23 */ | |
| 579 | #define CONFIG_SYS_ATA_ALT_OFFSET (0x00D8) | |
| 580 | ||
| 581 | /* Interval between registers */ | |
| 582 | #define CONFIG_SYS_ATA_STRIDE 4 | |
| 583 | ||
| 584 | #define ATA_BASE_ADDR get_pata_base() | |
| 585 | ||
| 586 | /* | |
| 587 | * Control register bit definitions | |
| 588 | */ | |
| 589 | #define FSL_ATA_CTRL_FIFO_RST_B 0x80000000 | |
| 590 | #define FSL_ATA_CTRL_ATA_RST_B 0x40000000 | |
| 591 | #define FSL_ATA_CTRL_FIFO_TX_EN 0x20000000 | |
| 592 | #define FSL_ATA_CTRL_FIFO_RCV_EN 0x10000000 | |
| 593 | #define FSL_ATA_CTRL_DMA_PENDING 0x08000000 | |
| 594 | #define FSL_ATA_CTRL_DMA_ULTRA 0x04000000 | |
| 595 | #define FSL_ATA_CTRL_DMA_WRITE 0x02000000 | |
| 596 | #define FSL_ATA_CTRL_IORDY_EN 0x01000000 | |
| 597 | ||
| e5f53864 AG |
598 | /* Clocks in use */ |
| 599 | #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ | |
| 600 | CLOCK_SCCR1_LPC_EN | \ | |
| 601 | CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \ | |
| 602 | CLOCK_SCCR1_PSCFIFO_EN | \ | |
| 603 | CLOCK_SCCR1_DDR_EN | \ | |
| 604 | CLOCK_SCCR1_FEC_EN | \ | |
| 605 | CLOCK_SCCR1_NFC_EN | \ | |
| 606 | CLOCK_SCCR1_PATA_EN | \ | |
| 607 | CLOCK_SCCR1_PCI_EN | \ | |
| 608 | CLOCK_SCCR1_TPR_EN) | |
| 609 | ||
| 610 | #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \ | |
| 611 | CLOCK_SCCR2_SPDIF_EN | \ | |
| 612 | CLOCK_SCCR2_DIU_EN | \ | |
| 613 | CLOCK_SCCR2_I2C_EN) | |
| 614 | ||
| 52568c36 | 615 | #endif /* __CONFIG_H */ |