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6afcabf1 | 1 | /* |
983c1db0 | 2 | * (C) Copyright 2007-2008 |
567fb852 | 3 | * Stelian Pop <stelian.pop@leadtechdesign.com> |
6afcabf1 SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
6 | * Configuation settings for the AT91CAP9ADK board. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* ARM asynchronous clock */ | |
c139b17d | 31 | #define AT91_CPU_NAME "AT91CAP9" |
ad229a44 SP |
32 | #define AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
33 | #define AT91_MASTER_CLOCK 100000000 /* peripheral */ | |
34 | #define AT91_CPU_CLOCK 200000000 /* cpu */ | |
9e2a79b4 | 35 | #define CONFIG_SYS_AT91_PLLB 0x10073e01 /* PLLB settings for USB */ |
ad229a44 | 36 | #define CONFIG_SYS_HZ 1000000 /* 1us resolution */ |
6afcabf1 SP |
37 | |
38 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | |
39 | ||
40 | #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ | |
41 | #define CONFIG_AT91CAP9 1 /* It's an Atmel AT91CAP9 SoC */ | |
42 | #define CONFIG_AT91CAP9ADK 1 /* on an AT91CAP9ADK Board */ | |
43 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
44 | ||
45 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
46 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
47 | #define CONFIG_INITRD_TAG 1 | |
48 | ||
49 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
50 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
51 | ||
6afcabf1 SP |
52 | /* |
53 | * Hardware drivers | |
54 | */ | |
6afcabf1 SP |
55 | #define CONFIG_ATMEL_USART 1 |
56 | #undef CONFIG_USART0 | |
57 | #undef CONFIG_USART1 | |
58 | #undef CONFIG_USART2 | |
59 | #define CONFIG_USART3 1 /* USART 3 is DBGU */ | |
60 | ||
c139b17d SP |
61 | /* LCD */ |
62 | #define CONFIG_LCD 1 | |
63 | #define LCD_BPP LCD_COLOR8 | |
64 | #define CONFIG_LCD_LOGO 1 | |
65 | #undef LCD_TEST_PATTERN | |
66 | #define CONFIG_LCD_INFO 1 | |
67 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
6d0f6bcf | 68 | #define CONFIG_SYS_WHITE_ON_BLACK 1 |
c139b17d SP |
69 | #define CONFIG_ATMEL_LCD 1 |
70 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
6d0f6bcf | 71 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
c139b17d | 72 | |
6afcabf1 | 73 | #define CONFIG_BOOTDELAY 3 |
6afcabf1 | 74 | |
6afcabf1 SP |
75 | /* |
76 | * BOOTP options | |
77 | */ | |
78 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
79 | #define CONFIG_BOOTP_BOOTPATH 1 | |
80 | #define CONFIG_BOOTP_GATEWAY 1 | |
81 | #define CONFIG_BOOTP_HOSTNAME 1 | |
82 | ||
83 | /* | |
84 | * Command line configuration. | |
85 | */ | |
86 | #include <config_cmd_default.h> | |
87 | #undef CONFIG_CMD_BDI | |
88 | #undef CONFIG_CMD_IMI | |
89 | #undef CONFIG_CMD_AUTOSCRIPT | |
90 | #undef CONFIG_CMD_FPGA | |
91 | #undef CONFIG_CMD_LOADS | |
92 | ||
93 | #define CONFIG_CMD_PING 1 | |
94 | #define CONFIG_CMD_DHCP 1 | |
95 | #define CONFIG_CMD_NAND 1 | |
96 | #define CONFIG_CMD_USB 1 | |
97 | ||
98 | /* SDRAM: Careful: this supposes an AT91CAP-MEM33 expansion card */ | |
99 | #define CONFIG_NR_DRAM_BANKS 1 | |
100 | #define PHYS_SDRAM 0x70000000 | |
101 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
102 | ||
103 | /* DataFlash */ | |
104 | #define CONFIG_HAS_DATAFLASH 1 | |
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ) |
106 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 | |
107 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
93da48b9 SP |
108 | #define AT91_SPI_CLK 15000000 |
109 | #define DATAFLASH_TCSS (0x1a << 16) | |
110 | #define DATAFLASH_TCHS (0x1 << 24) | |
6afcabf1 SP |
111 | |
112 | /* NOR flash */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 114 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6afcabf1 | 115 | #define PHYS_FLASH_1 0x10000000 |
6d0f6bcf JCPV |
116 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
117 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
6afcabf1 | 119 | |
6afcabf1 | 120 | /* NAND flash */ |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
122 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
123 | #define CONFIG_SYS_NAND_DBW_8 1 | |
6afcabf1 | 124 | |
6afcabf1 SP |
125 | /* Ethernet */ |
126 | #define CONFIG_MACB 1 | |
127 | #define CONFIG_RMII 1 | |
128 | #define CONFIG_NET_MULTI 1 | |
129 | #define CONFIG_NET_RETRY_COUNT 20 | |
130 | #define CONFIG_RESET_PHY_R 1 | |
131 | ||
132 | /* USB */ | |
133 | #define CONFIG_USB_OHCI_NEW 1 | |
6afcabf1 | 134 | #define CONFIG_DOS_PARTITION 1 |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
136 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* AT91_BASE_UHP */ | |
137 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91cap9" | |
138 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
3e0cda07 SP |
139 | #define CONFIG_USB_STORAGE 1 |
140 | #define CONFIG_CMD_FAT 1 | |
6afcabf1 | 141 | |
6d0f6bcf | 142 | #define CONFIG_SYS_LOAD_ADDR 0x72000000 /* load address */ |
6afcabf1 | 143 | |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM |
145 | #define CONFIG_SYS_MEMTEST_END 0x73e00000 | |
6afcabf1 | 146 | |
6d0f6bcf JCPV |
147 | #define CONFIG_SYS_USE_DATAFLASH 1 |
148 | #undef CONFIG_SYS_USE_NORFLASH | |
6afcabf1 | 149 | |
6d0f6bcf | 150 | #ifdef CONFIG_SYS_USE_DATAFLASH |
6afcabf1 SP |
151 | |
152 | /* bootstrap + u-boot + env + linux in dataflash */ | |
057c849c | 153 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 |
6d0f6bcf | 154 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
0e8d1586 | 155 | #define CONFIG_ENV_OFFSET 0x4200 |
6d0f6bcf | 156 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
0e8d1586 | 157 | #define CONFIG_ENV_SIZE 0x4200 |
ab52640f | 158 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x72000000 0x210000; bootm" |
3267508e SP |
159 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
160 | "root=/dev/mtdblock1 " \ | |
161 | "mtdparts=physmap-flash.0:-(nor);" \ | |
162 | "at91_nand:-(root) " \ | |
163 | "rw rootfstype=jffs2" | |
6afcabf1 SP |
164 | |
165 | #else | |
166 | ||
167 | /* bootstrap + u-boot + env + linux in norflash */ | |
5a1aceb0 | 168 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 169 | #define CONFIG_SYS_MONITOR_BASE (PHYS_FLASH_1 + 0x8000) |
0e8d1586 JCPV |
170 | #define CONFIG_ENV_OFFSET 0x4000 |
171 | #define CONFIG_ENV_ADDR (PHYS_FLASH_1 + CONFIG_ENV_OFFSET) | |
172 | #define CONFIG_ENV_SIZE 0x4000 | |
6afcabf1 | 173 | #define CONFIG_BOOTCOMMAND "cp.b 0x10040000 0x72000000 0x200000; bootm" |
3267508e SP |
174 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
175 | "root=/dev/mtdblock4 " \ | |
176 | "mtdparts=physmap-flash.0:16k(bootstrap)ro,"\ | |
177 | "16k(env),224k(uboot)ro,-(linux);" \ | |
178 | "at91_nand:-(root) " \ | |
179 | "rw rootfstype=jffs2" | |
6afcabf1 SP |
180 | |
181 | #endif | |
182 | ||
983c1db0 | 183 | #define CONFIG_BAUDRATE 115200 |
6d0f6bcf | 184 | #define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } |
6afcabf1 | 185 | |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_PROMPT "U-Boot> " |
187 | #define CONFIG_SYS_CBSIZE 256 | |
188 | #define CONFIG_SYS_MAXARGS 16 | |
189 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) | |
190 | #define CONFIG_SYS_LONGHELP 1 | |
6afcabf1 SP |
191 | #define CONFIG_CMDLINE_EDITING 1 |
192 | ||
983c1db0 SP |
193 | #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) |
194 | /* | |
195 | * Size of malloc() pool | |
196 | */ | |
6d0f6bcf JCPV |
197 | #define CONFIG_SYS_MALLOC_LEN ROUND(CONFIG_ENV_SIZE + 128*1024, 0x1000) |
198 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ | |
983c1db0 | 199 | |
6afcabf1 SP |
200 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ |
201 | ||
202 | #ifdef CONFIG_USE_IRQ | |
203 | #error CONFIG_USE_IRQ not supported | |
204 | #endif | |
205 | ||
206 | #endif |