[people/ms/u-boot.git] / include / configs / at91sam9260ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
#define CONFIG_SYS_AT91_PLLB	0x107c3e18	/* PLLB settings for USB */
#define CONFIG_SYS_HZ		1000000		/* 1us resolution */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/

#ifdef CONFIG_AT91SAM9G20EK
#define AT91_CPU_NAME		"AT91SAM9G20"
#define AT91_MASTER_CLOCK	132000000	/* peripheral */
#define AT91_CPU_CLOCK		396000000	/* cpu */
#define CONFIG_AT91SAM9G20	1	/* It's an Atmel AT91SAM9G20 SoC*/
#else
#define AT91_CPU_NAME		"AT91SAM9260"
#define AT91_MASTER_CLOCK	100000000	/* peripheral */
#define AT91_CPU_CLOCK		200000000	/* cpu */
#define CONFIG_AT91SAM9260	1	/* It's an Atmel AT91SAM9260 SoC*/
#endif

#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_USART	1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3		1	/* USART 3 is DBGU */

/* LED */
#define CONFIG_AT91_LED
#define	CONFIG_RED_LED		AT91_PIN_PA9	/* this is the power led */
#define	CONFIG_GREEN_LED	AT91_PIN_PA6	/* this is the user led */

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_SOURCE

#define CONFIG_CMD_PING		1
#define CONFIG_CMD_DHCP		1
#define CONFIG_CMD_NAND		1
#define CONFIG_CMD_USB		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x20000000
#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_HAS_DATAFLASH		1
#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1	0xD0000000	/* CS1 */
#define AT91_SPI_CLK			15000000

#ifdef CONFIG_AT91SAM9G20EK
#define DATAFLASH_TCSS			(0x22 << 16)
#else
#define DATAFLASH_TCSS			(0x1a << 16)
#endif
#define DATAFLASH_TCHS			(0x1 << 24)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC13
#endif

/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH			1

/* Ethernet */
#define CONFIG_MACB			1
#define CONFIG_RMII			1
#define CONFIG_NET_MULTI		1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1

/* USB */
#define CONFIG_USB_OHCI_NEW		1
#define CONFIG_DOS_PARTITION		1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9260_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE		1
#define CONFIG_CMD_FAT			1

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH	1
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET		0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=at91_nand:-(root) "		\
				"rw rootfstype=jffs2"

#elif CONFIG_SYS_USE_DATAFLASH_CS1

/* bootstrap + u-boot + env + linux in dataflash on CS1 */
#define CONFIG_ENV_IS_IN_DATAFLASH	1
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
#define CONFIG_ENV_OFFSET		0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xD0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=at91_nand:-(root) "		\
				"rw rootfstype=jffs2"

#else /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND	1
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock5 "			\
				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
				"256k(uboot)ro,128k(env1)ro,"		\
				"128k(env2)ro,2M(linux),-(root) "	\
				"rw rootfstype=jffs2"

#endif

#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"U-Boot> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
0176d43e SP	1	/*
0176d43e SP	2	* (C) Copyright 2007-2008
567fb852	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
0176d43e SP	4	* Lead Tech Design <www.leadtechdesign.com>
0176d43e SP	5	*
df486b1f	6	* Configuation settings for the AT91SAM9260EK & AT91SAM9G20EK boards.
0176d43e SP	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/* ARM asynchronous clock */
ad229a44	31	#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
3aed3aa2	32	#define CONFIG_SYS_AT91_PLLB 0x107c3e18 /* PLLB settings for USB */
ad229a44	33	#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
0176d43e SP	34
	35	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	36
	37	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
df486b1f NF	38
	39	#ifdef CONFIG_AT91SAM9G20EK
	40	#define AT91_CPU_NAME "AT91SAM9G20"
	41	#define AT91_MASTER_CLOCK 132000000 /* peripheral */
	42	#define AT91_CPU_CLOCK 396000000 /* cpu */
	43	#define CONFIG_AT91SAM9G20 1 /* It's an Atmel AT91SAM9G20 SoC*/
	44	#else
	45	#define AT91_CPU_NAME "AT91SAM9260"
	46	#define AT91_MASTER_CLOCK 100000000 /* peripheral */
	47	#define AT91_CPU_CLOCK 200000000 /* cpu */
0176d43e	48	#define CONFIG_AT91SAM9260 1 /* It's an Atmel AT91SAM9260 SoC*/
df486b1f NF	49	#endif
df486b1f NF	50
0176d43e SP	51	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	52
	53	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	54	#define CONFIG_SETUP_MEMORY_TAGS 1
	55	#define CONFIG_INITRD_TAG 1
	56
	57	#define CONFIG_SKIP_LOWLEVEL_INIT
	58	#define CONFIG_SKIP_RELOCATE_UBOOT
	59
	60	/*
	61	* Hardware drivers
	62	*/
	63	#define CONFIG_ATMEL_USART 1
	64	#undef CONFIG_USART0
	65	#undef CONFIG_USART1
	66	#undef CONFIG_USART2
	67	#define CONFIG_USART3 1 /* USART 3 is DBGU */
	68
a484b00b JCPV	69	/* LED */
	70	#define CONFIG_AT91_LED
	71	#define CONFIG_RED_LED AT91_PIN_PA9 /* this is the power led */
	72	#define CONFIG_GREEN_LED AT91_PIN_PA6 /* this is the user led */
	73
0176d43e	74	#define CONFIG_BOOTDELAY 3
0176d43e	75
0176d43e SP	76	/*
	77	* BOOTP options
	78	*/
	79	#define CONFIG_BOOTP_BOOTFILESIZE 1
	80	#define CONFIG_BOOTP_BOOTPATH 1
	81	#define CONFIG_BOOTP_GATEWAY 1
	82	#define CONFIG_BOOTP_HOSTNAME 1
	83
	84	/*
	85	* Command line configuration.
	86	*/
	87	#include <config_cmd_default.h>
	88	#undef CONFIG_CMD_BDI
0176d43e	89	#undef CONFIG_CMD_FPGA
74de7aef	90	#undef CONFIG_CMD_IMI
0176d43e	91	#undef CONFIG_CMD_IMLS
74de7aef WD	92	#undef CONFIG_CMD_LOADS
74de7aef WD	93	#undef CONFIG_CMD_SOURCE
0176d43e SP	94
	95	#define CONFIG_CMD_PING 1
	96	#define CONFIG_CMD_DHCP 1
	97	#define CONFIG_CMD_NAND 1
	98	#define CONFIG_CMD_USB 1
	99
	100	/* SDRAM */
	101	#define CONFIG_NR_DRAM_BANKS 1
	102	#define PHYS_SDRAM 0x20000000
	103	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	104
	105	/* DataFlash */
	106	#define CONFIG_HAS_DATAFLASH 1
6d0f6bcf JCPV	107	#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
	108	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
	109	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
	110	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 0xD0000000 /* CS1 */
79f0cb6e	111	#define AT91_SPI_CLK 15000000
df486b1f NF	112
	113	#ifdef CONFIG_AT91SAM9G20EK
	114	#define DATAFLASH_TCSS (0x22 << 16)
	115	#else
0176d43e	116	#define DATAFLASH_TCSS (0x1a << 16)
df486b1f	117	#endif
0176d43e SP	118	#define DATAFLASH_TCHS (0x1 << 24)
	119
	120	/* NAND flash */
74c076d6 JCPV	121	#ifdef CONFIG_CMD_NAND
74c076d6 JCPV	122	#define CONFIG_NAND_ATMEL
6d0f6bcf JCPV	123	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	124	#define CONFIG_SYS_NAND_BASE 0x40000000
	125	#define CONFIG_SYS_NAND_DBW_8 1
74c076d6 JCPV	126	/* our ALE is AD21 */
	127	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	128	/* our CLE is AD22 */
	129	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	130	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	131	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
	132	#endif
0176d43e SP	133
0176d43e SP	134	/* NOR flash - no real flash on this board */
6d0f6bcf	135	#define CONFIG_SYS_NO_FLASH 1
0176d43e SP	136
	137	/* Ethernet */
	138	#define CONFIG_MACB 1
	139	#define CONFIG_RMII 1
	140	#define CONFIG_NET_MULTI 1
	141	#define CONFIG_NET_RETRY_COUNT 20
	142	#define CONFIG_RESET_PHY_R 1
	143
	144	/* USB */
	145	#define CONFIG_USB_OHCI_NEW 1
0176d43e	146	#define CONFIG_DOS_PARTITION 1
6d0f6bcf JCPV	147	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	148	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */
	149	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
	150	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
0176d43e	151	#define CONFIG_USB_STORAGE 1
3e0cda07	152	#define CONFIG_CMD_FAT 1
0176d43e	153
6d0f6bcf	154	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
0176d43e	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
6d0f6bcf JCPV	157	#define CONFIG_SYS_MEMTEST_END 0x23e00000
0176d43e	158
6d0f6bcf	159	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
0176d43e SP	160
0176d43e SP	161	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
057c849c	162	#define CONFIG_ENV_IS_IN_DATAFLASH 1
6d0f6bcf	163	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
0e8d1586	164	#define CONFIG_ENV_OFFSET 0x4200
6d0f6bcf	165	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586	166	#define CONFIG_ENV_SIZE 0x4200
86c8c8a4	167	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
96996ac2 SP	168	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	169	"root=/dev/mtdblock0 " \
	170	"mtdparts=at91_nand:-(root) " \
	171	"rw rootfstype=jffs2"
0176d43e	172
6d0f6bcf	173	#elif CONFIG_SYS_USE_DATAFLASH_CS1
0176d43e SP	174
0176d43e SP	175	/* bootstrap + u-boot + env + linux in dataflash on CS1 */
057c849c	176	#define CONFIG_ENV_IS_IN_DATAFLASH 1
6d0f6bcf	177	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + 0x8400)
0e8d1586	178	#define CONFIG_ENV_OFFSET 0x4200
6d0f6bcf	179	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1 + CONFIG_ENV_OFFSET)
0e8d1586	180	#define CONFIG_ENV_SIZE 0x4200
86c8c8a4	181	#define CONFIG_BOOTCOMMAND "cp.b 0xD0042000 0x22000000 0x210000; bootm"
96996ac2 SP	182	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	183	"root=/dev/mtdblock0 " \
	184	"mtdparts=at91_nand:-(root) " \
	185	"rw rootfstype=jffs2"
0176d43e	186
6d0f6bcf	187	#else /* CONFIG_SYS_USE_NANDFLASH */
0176d43e SP	188
0176d43e SP	189	/* bootstrap + u-boot + env + linux in nandflash */
51bfee19	190	#define CONFIG_ENV_IS_IN_NAND 1
0e8d1586 JCPV	191	#define CONFIG_ENV_OFFSET 0x60000
	192	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	193	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
0176d43e	194	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
96996ac2 SP	195	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	196	"root=/dev/mtdblock5 " \
	197	"mtdparts=at91_nand:128k(bootstrap)ro," \
	198	"256k(uboot)ro,128k(env1)ro," \
	199	"128k(env2)ro,2M(linux),-(root) " \
	200	"rw rootfstype=jffs2"
0176d43e SP	201
	202	#endif
	203
	204	#define CONFIG_BAUDRATE 115200
6d0f6bcf	205	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
0176d43e	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_PROMPT "U-Boot> "
	208	#define CONFIG_SYS_CBSIZE 256
	209	#define CONFIG_SYS_MAXARGS 16
	210	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	211	#define CONFIG_SYS_LONGHELP 1
0176d43e SP	212	#define CONFIG_CMDLINE_EDITING 1
	213
	214	#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
	215	/*
	216	* Size of malloc() pool
	217	*/
6d0f6bcf JCPV	218	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
6d0f6bcf JCPV	219	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
0176d43e SP	220
	221	#define CONFIG_STACKSIZE (321024) / regular stack */
	222
	223	#ifdef CONFIG_USE_IRQ
	224	#error CONFIG_USE_IRQ not supported
	225	#endif
	226
	227	#endif