[people/ms/u-boot.git] / include / configs / at91sam9261ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian.pop@leadtechdesign.com>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9261EK board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* ARM asynchronous clock */
#define AT91_CPU_NAME		"AT91SAM9261"
#define AT91_MAIN_CLOCK		18432000	/* 18.432 MHz crystal */
#define AT91_MASTER_CLOCK	100000000	/* peripheral */
#define AT91_CPU_CLOCK		200000000	/* cpu */
#define CONFIG_SYS_HZ		1000000		/* 1us resolution */

#define AT91_SLOW_CLOCK		32768	/* slow clock */

#define CONFIG_ARM926EJS	1	/* This is an ARM926EJS Core	*/
#define CONFIG_AT91SAM9261	1	/* It's an Atmel AT91SAM9261 SoC*/
#define CONFIG_AT91SAM9261EK	1	/* on an AT91SAM9261EK Board	*/
#undef CONFIG_USE_IRQ			/* we don't need IRQ/FIQ stuff	*/

#define CONFIG_CMDLINE_TAG	1	/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS 1
#define CONFIG_INITRD_TAG	1

#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_SKIP_RELOCATE_UBOOT

/*
 * Hardware drivers
 */
#define CONFIG_ATMEL_USART	1
#undef CONFIG_USART0
#undef CONFIG_USART1
#undef CONFIG_USART2
#define CONFIG_USART3		1	/* USART 3 is DBGU */

/* LCD */
#define CONFIG_LCD			1
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO			1
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO			1
#define CONFIG_LCD_INFO_BELOW_LOGO	1
#define CONFIG_SYS_WHITE_ON_BLACK		1
#define CONFIG_ATMEL_LCD		1
#define CONFIG_ATMEL_LCD_BGR555		1
#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1

#define CONFIG_BOOTDELAY	3

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE	1
#define CONFIG_BOOTP_BOOTPATH		1
#define CONFIG_BOOTP_GATEWAY		1
#define CONFIG_BOOTP_HOSTNAME		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#undef CONFIG_CMD_BDI
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_IMLS

#define CONFIG_CMD_PING		1
#define CONFIG_CMD_DHCP		1
#define CONFIG_CMD_NAND		1
#define CONFIG_CMD_USB		1

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM			0x20000000
#define PHYS_SDRAM_SIZE			0x04000000	/* 64 megs */

/* DataFlash */
#define CONFIG_HAS_DATAFLASH		1
#define CONFIG_SYS_SPI_WRITE_TOUT		(5*CONFIG_SYS_HZ)
#define CONFIG_SYS_MAX_DATAFLASH_BANKS		2
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0	0xC0000000	/* CS0 */
#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3	0xD0000000	/* CS3 */
#define AT91_SPI_CLK			15000000
#define DATAFLASH_TCSS			(0x1a << 16)
#define DATAFLASH_TCHS			(0x1 << 24)

/* NAND flash */
#define NAND_MAX_CHIPS			1
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			0x40000000
#define CONFIG_SYS_NAND_DBW_8			1

/* NOR flash - no real flash on this board */
#define CONFIG_SYS_NO_FLASH			1

/* Ethernet */
#define CONFIG_DRIVER_DM9000		1
#define CONFIG_DM9000_BASE		0x30000000
#define DM9000_IO			CONFIG_DM9000_BASE
#define DM9000_DATA			(CONFIG_DM9000_BASE + 4)
#define CONFIG_DM9000_USE_16BIT		1
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R		1

/* USB */
#define CONFIG_USB_OHCI_NEW		1
#define LITTLEENDIAN			1
#define CONFIG_DOS_PARTITION		1
#define CONFIG_SYS_USB_OHCI_CPU_INIT		1
#define CONFIG_SYS_USB_OHCI_REGS_BASE		0x00500000	/* AT91SAM9261_UHP_BASE */
#define CONFIG_SYS_USB_OHCI_SLOT_NAME		"at91sam9261"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2
#define CONFIG_USB_STORAGE		1

#define CONFIG_SYS_LOAD_ADDR			0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START		PHYS_SDRAM
#define CONFIG_SYS_MEMTEST_END			0x23e00000

#define CONFIG_SYS_USE_DATAFLASH_CS0		1
#undef CONFIG_SYS_USE_NANDFLASH

#ifdef CONFIG_SYS_USE_DATAFLASH_CS0

/* bootstrap + u-boot + env + linux in dataflash on CS0 */
#define CONFIG_ENV_IS_IN_DATAFLASH	1
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
#define CONFIG_ENV_OFFSET		0x4200
#define CONFIG_ENV_ADDR		(CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x4200
#define CONFIG_BOOTCOMMAND	"cp.b 0xC0042000 0x22000000 0x210000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock0 "			\
				"mtdparts=at91_nand:-(root) "		\
				"rw rootfstype=jffs2"

#else /* CONFIG_SYS_USE_NANDFLASH */

/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_IS_IN_NAND	1
#define CONFIG_ENV_OFFSET		0x60000
#define CONFIG_ENV_OFFSET_REDUND	0x80000
#define CONFIG_ENV_SIZE		0x20000		/* 1 sector = 128 kB */
#define CONFIG_BOOTCOMMAND	"nand read 0x22000000 0xA0000 0x200000; bootm"
#define CONFIG_BOOTARGS		"console=ttyS0,115200 "			\
				"root=/dev/mtdblock5 "			\
				"mtdparts=at91_nand:128k(bootstrap)ro,"	\
				"256k(uboot)ro,128k(env1)ro,"		\
				"128k(env2)ro,2M(linux),-(root) "	\
				"rw rootfstype=jffs2"

#endif

#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{115200 , 19200, 38400, 57600, 9600 }

#define CONFIG_SYS_PROMPT		"U-Boot> "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#define ROUND(A, B)		(((A) + (B)) & ~((B) - 1))
/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* 128 bytes for initial data */

#define CONFIG_STACKSIZE	(32*1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif
Commit	Line	Data
d99a8ff6 SP	1	/*
	2	* (C) Copyright 2007-2008
	3	* Stelian Pop <stelian.pop@leadtechdesign.com>
	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91SAM9261EK board.
	7	*
	8	* See file CREDITS for list of people who contributed to this
	9	* project.
	10	*
	11	* This program is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of
	14	* the License, or (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* You should have received a copy of the GNU General Public License
	22	* along with this program; if not, write to the Free Software
	23	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	24	* MA 02111-1307 USA
	25	*/
	26
	27	#ifndef __CONFIG_H
	28	#define __CONFIG_H
	29
	30	/* ARM asynchronous clock */
820f2a95	31	#define AT91_CPU_NAME "AT91SAM9261"
ad229a44 SP	32	#define AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
	33	#define AT91_MASTER_CLOCK 100000000 /* peripheral */
	34	#define AT91_CPU_CLOCK 200000000 /* cpu */
	35	#define CONFIG_SYS_HZ 1000000 /* 1us resolution */
d99a8ff6 SP	36
	37	#define AT91_SLOW_CLOCK 32768 /* slow clock */
	38
	39	#define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */
	40	#define CONFIG_AT91SAM9261 1 /* It's an Atmel AT91SAM9261 SoC*/
	41	#define CONFIG_AT91SAM9261EK 1 /* on an AT91SAM9261EK Board */
	42	#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
	43
	44	#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
	45	#define CONFIG_SETUP_MEMORY_TAGS 1
	46	#define CONFIG_INITRD_TAG 1
	47
	48	#define CONFIG_SKIP_LOWLEVEL_INIT
	49	#define CONFIG_SKIP_RELOCATE_UBOOT
	50
	51	/*
	52	* Hardware drivers
	53	*/
	54	#define CONFIG_ATMEL_USART 1
	55	#undef CONFIG_USART0
	56	#undef CONFIG_USART1
	57	#undef CONFIG_USART2
	58	#define CONFIG_USART3 1 /* USART 3 is DBGU */
	59
820f2a95 SP	60	/* LCD */
	61	#define CONFIG_LCD 1
	62	#define LCD_BPP LCD_COLOR8
	63	#define CONFIG_LCD_LOGO 1
	64	#undef LCD_TEST_PATTERN
	65	#define CONFIG_LCD_INFO 1
	66	#define CONFIG_LCD_INFO_BELOW_LOGO 1
6d0f6bcf	67	#define CONFIG_SYS_WHITE_ON_BLACK 1
820f2a95 SP	68	#define CONFIG_ATMEL_LCD 1
820f2a95 SP	69	#define CONFIG_ATMEL_LCD_BGR555 1
6d0f6bcf	70	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
820f2a95	71
d99a8ff6 SP	72	#define CONFIG_BOOTDELAY 3
d99a8ff6 SP	73
d99a8ff6 SP	74	/*
	75	* BOOTP options
	76	*/
	77	#define CONFIG_BOOTP_BOOTFILESIZE 1
	78	#define CONFIG_BOOTP_BOOTPATH 1
	79	#define CONFIG_BOOTP_GATEWAY 1
	80	#define CONFIG_BOOTP_HOSTNAME 1
	81
	82	/*
	83	* Command line configuration.
	84	*/
	85	#include <config_cmd_default.h>
	86	#undef CONFIG_CMD_BDI
	87	#undef CONFIG_CMD_IMI
	88	#undef CONFIG_CMD_AUTOSCRIPT
	89	#undef CONFIG_CMD_FPGA
	90	#undef CONFIG_CMD_LOADS
	91	#undef CONFIG_CMD_IMLS
	92
	93	#define CONFIG_CMD_PING 1
	94	#define CONFIG_CMD_DHCP 1
	95	#define CONFIG_CMD_NAND 1
	96	#define CONFIG_CMD_USB 1
	97
	98	/* SDRAM */
	99	#define CONFIG_NR_DRAM_BANKS 1
	100	#define PHYS_SDRAM 0x20000000
	101	#define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
	102
	103	/* DataFlash */
	104	#define CONFIG_HAS_DATAFLASH 1
6d0f6bcf JCPV	105	#define CONFIG_SYS_SPI_WRITE_TOUT (5*CONFIG_SYS_HZ)
	106	#define CONFIG_SYS_MAX_DATAFLASH_BANKS 2
	107	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */
	108	#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3 0xD0000000 /* CS3 */
d99a8ff6 SP	109	#define AT91_SPI_CLK 15000000
	110	#define DATAFLASH_TCSS (0x1a << 16)
	111	#define DATAFLASH_TCHS (0x1 << 24)
	112
	113	/* NAND flash */
	114	#define NAND_MAX_CHIPS 1
6d0f6bcf JCPV	115	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	116	#define CONFIG_SYS_NAND_BASE 0x40000000
	117	#define CONFIG_SYS_NAND_DBW_8 1
d99a8ff6 SP	118
d99a8ff6 SP	119	/* NOR flash - no real flash on this board */
6d0f6bcf	120	#define CONFIG_SYS_NO_FLASH 1
d99a8ff6 SP	121
	122	/* Ethernet */
	123	#define CONFIG_DRIVER_DM9000 1
	124	#define CONFIG_DM9000_BASE 0x30000000
	125	#define DM9000_IO CONFIG_DM9000_BASE
	126	#define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	127	#define CONFIG_DM9000_USE_16BIT 1
	128	#define CONFIG_NET_RETRY_COUNT 20
	129	#define CONFIG_RESET_PHY_R 1
	130
	131	/* USB */
	132	#define CONFIG_USB_OHCI_NEW 1
	133	#define LITTLEENDIAN 1
	134	#define CONFIG_DOS_PARTITION 1
6d0f6bcf JCPV	135	#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
	136	#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */
	137	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261"
	138	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
d99a8ff6 SP	139	#define CONFIG_USB_STORAGE 1
d99a8ff6 SP	140
6d0f6bcf	141	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
d99a8ff6	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
6d0f6bcf JCPV	144	#define CONFIG_SYS_MEMTEST_END 0x23e00000
d99a8ff6	145
6d0f6bcf JCPV	146	#define CONFIG_SYS_USE_DATAFLASH_CS0 1
6d0f6bcf JCPV	147	#undef CONFIG_SYS_USE_NANDFLASH
d99a8ff6	148
6d0f6bcf	149	#ifdef CONFIG_SYS_USE_DATAFLASH_CS0
d99a8ff6 SP	150
d99a8ff6 SP	151	/* bootstrap + u-boot + env + linux in dataflash on CS0 */
057c849c	152	#define CONFIG_ENV_IS_IN_DATAFLASH 1
6d0f6bcf	153	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400)
0e8d1586	154	#define CONFIG_ENV_OFFSET 0x4200
6d0f6bcf	155	#define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
0e8d1586	156	#define CONFIG_ENV_SIZE 0x4200
d99a8ff6 SP	157	#define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm"
	158	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	159	"root=/dev/mtdblock0 " \
	160	"mtdparts=at91_nand:-(root) " \
	161	"rw rootfstype=jffs2"
	162
6d0f6bcf	163	#else /* CONFIG_SYS_USE_NANDFLASH */
d99a8ff6 SP	164
d99a8ff6 SP	165	/* bootstrap + u-boot + env + linux in nandflash */
51bfee19	166	#define CONFIG_ENV_IS_IN_NAND 1
0e8d1586 JCPV	167	#define CONFIG_ENV_OFFSET 0x60000
	168	#define CONFIG_ENV_OFFSET_REDUND 0x80000
	169	#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
d99a8ff6 SP	170	#define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm"
	171	#define CONFIG_BOOTARGS "console=ttyS0,115200 " \
	172	"root=/dev/mtdblock5 " \
	173	"mtdparts=at91_nand:128k(bootstrap)ro," \
	174	"256k(uboot)ro,128k(env1)ro," \
	175	"128k(env2)ro,2M(linux),-(root) " \
	176	"rw rootfstype=jffs2"
	177
	178	#endif
	179
	180	#define CONFIG_BAUDRATE 115200
6d0f6bcf	181	#define CONFIG_SYS_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 }
d99a8ff6	182
6d0f6bcf JCPV	183	#define CONFIG_SYS_PROMPT "U-Boot> "
	184	#define CONFIG_SYS_CBSIZE 256
	185	#define CONFIG_SYS_MAXARGS 16
	186	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	187	#define CONFIG_SYS_LONGHELP 1
d99a8ff6 SP	188	#define CONFIG_CMDLINE_EDITING 1
	189
	190	#define ROUND(A, B) (((A) + (B)) & ~((B) - 1))
	191	/*
	192	* Size of malloc() pool
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
6d0f6bcf JCPV	195	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* 128 bytes for initial data */
d99a8ff6 SP	196
	197	#define CONFIG_STACKSIZE (321024) / regular stack */
	198
	199	#ifdef CONFIG_USE_IRQ
	200	#error CONFIG_USE_IRQ not supported
	201	#endif
	202
	203	#endif