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d99a8ff6 SP |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
d99a8ff6 SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
6 | * Configuation settings for the AT91SAM9261EK board. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
d99a8ff6 SP |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* ARM asynchronous clock */ | |
f7aea46d | 15 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
7c966a8b | 16 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */ |
d99a8ff6 | 17 | |
f7aea46d XH |
18 | #ifdef CONFIG_AT91SAM9G10 |
19 | #define CONFIG_AT91SAM9G10EK /* It's an Atmel AT91SAM9G10 EK*/ | |
5ccc2d99 | 20 | #else |
f7aea46d | 21 | #define CONFIG_AT91SAM9261EK /* It's an Atmel AT91SAM9261 EK*/ |
5ccc2d99 | 22 | #endif |
f7aea46d XH |
23 | |
24 | #include <asm/hardware.h> | |
25 | ||
f7aea46d XH |
26 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
27 | #define CONFIG_SETUP_MEMORY_TAGS | |
28 | #define CONFIG_INITRD_TAG | |
d99a8ff6 SP |
29 | |
30 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
d99a8ff6 | 31 | |
f7aea46d | 32 | #define CONFIG_ATMEL_LEGACY |
f7aea46d | 33 | |
d99a8ff6 SP |
34 | /* |
35 | * Hardware drivers | |
36 | */ | |
f7aea46d | 37 | |
820f2a95 | 38 | /* LCD */ |
820f2a95 | 39 | #define LCD_BPP LCD_COLOR8 |
f7aea46d | 40 | #define CONFIG_LCD_LOGO |
820f2a95 | 41 | #undef LCD_TEST_PATTERN |
f7aea46d XH |
42 | #define CONFIG_LCD_INFO |
43 | #define CONFIG_LCD_INFO_BELOW_LOGO | |
f7aea46d | 44 | #define CONFIG_ATMEL_LCD |
5ccc2d99 | 45 | #ifdef CONFIG_AT91SAM9261EK |
f7aea46d | 46 | #define CONFIG_ATMEL_LCD_BGR555 |
5ccc2d99 | 47 | #endif |
f7aea46d | 48 | |
d99a8ff6 SP |
49 | /* |
50 | * BOOTP options | |
51 | */ | |
f7aea46d | 52 | #define CONFIG_BOOTP_BOOTFILESIZE |
d99a8ff6 | 53 | |
d99a8ff6 SP |
54 | /* SDRAM */ |
55 | #define CONFIG_NR_DRAM_BANKS 1 | |
f7aea46d XH |
56 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
57 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
58 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
324873e7 | 59 | (ATMEL_BASE_SRAM + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
d99a8ff6 SP |
60 | |
61 | /* NAND flash */ | |
74c076d6 JCPV |
62 | #ifdef CONFIG_CMD_NAND |
63 | #define CONFIG_NAND_ATMEL | |
6d0f6bcf JCPV |
64 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
65 | #define CONFIG_SYS_NAND_BASE 0x40000000 | |
f7aea46d | 66 | #define CONFIG_SYS_NAND_DBW_8 |
74c076d6 JCPV |
67 | /* our ALE is AD22 */ |
68 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 22) | |
69 | /* our CLE is AD21 */ | |
70 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 21) | |
71 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
72 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC15 | |
2eb99ca8 | 73 | |
74c076d6 | 74 | #endif |
d99a8ff6 | 75 | |
d99a8ff6 | 76 | /* Ethernet */ |
f7aea46d | 77 | #define CONFIG_DRIVER_DM9000 |
d99a8ff6 SP |
78 | #define CONFIG_DM9000_BASE 0x30000000 |
79 | #define DM9000_IO CONFIG_DM9000_BASE | |
80 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
f7aea46d XH |
81 | #define CONFIG_DM9000_USE_16BIT |
82 | #define CONFIG_DM9000_NO_SROM | |
d99a8ff6 | 83 | #define CONFIG_NET_RETRY_COUNT 20 |
f7aea46d | 84 | #define CONFIG_RESET_PHY_R |
d99a8ff6 SP |
85 | |
86 | /* USB */ | |
2b7178af | 87 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 88 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
f7aea46d | 89 | #define CONFIG_USB_OHCI_NEW |
f7aea46d | 90 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
6d0f6bcf | 91 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9261_UHP_BASE */ |
5ccc2d99 SG |
92 | #ifdef CONFIG_AT91SAM9G10EK |
93 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g10" | |
94 | #else | |
6d0f6bcf | 95 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9261" |
5ccc2d99 | 96 | #endif |
6d0f6bcf | 97 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
d99a8ff6 | 98 | |
6d0f6bcf | 99 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
d99a8ff6 | 100 | |
f7aea46d | 101 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
6d0f6bcf | 102 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
d99a8ff6 | 103 | |
6d0f6bcf | 104 | #ifdef CONFIG_SYS_USE_DATAFLASH_CS0 |
d99a8ff6 SP |
105 | |
106 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
89a7a87f | 107 | #define CONFIG_ENV_OFFSET 0x4200 |
0e8d1586 | 108 | #define CONFIG_ENV_SIZE 0x4200 |
324873e7 WY |
109 | #define CONFIG_ENV_SECT_SIZE 0x210 |
110 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 | |
111 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ | |
112 | "sf read 0x22000000 0x84000 0x294000; " \ | |
113 | "bootm 0x22000000" | |
d99a8ff6 | 114 | |
89a7a87f NF |
115 | #elif CONFIG_SYS_USE_DATAFLASH_CS3 |
116 | ||
117 | /* bootstrap + u-boot + env + linux in dataflash on CS3 */ | |
89a7a87f | 118 | #define CONFIG_ENV_OFFSET 0x4200 |
89a7a87f | 119 | #define CONFIG_ENV_SIZE 0x4200 |
324873e7 WY |
120 | #define CONFIG_ENV_SECT_SIZE 0x210 |
121 | #define CONFIG_ENV_SPI_MAX_HZ 15000000 | |
122 | #define CONFIG_BOOTCOMMAND "sf probe 0:3; " \ | |
123 | "sf read 0x22000000 0x84000 0x294000; " \ | |
124 | "bootm 0x22000000" | |
89a7a87f | 125 | |
6d0f6bcf | 126 | #else /* CONFIG_SYS_USE_NANDFLASH */ |
d99a8ff6 SP |
127 | |
128 | /* bootstrap + u-boot + env + linux in nandflash */ | |
324873e7 | 129 | #define CONFIG_ENV_OFFSET 0x120000 |
0c58cfa9 | 130 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
0e8d1586 | 131 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
0c58cfa9 | 132 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
d99a8ff6 SP |
133 | #endif |
134 | ||
d99a8ff6 SP |
135 | /* |
136 | * Size of malloc() pool | |
137 | */ | |
6d0f6bcf | 138 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
d99a8ff6 | 139 | |
d99a8ff6 | 140 | #endif |