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1 | /* |
2 | * (C) Copyright 2007-2008 | |
3 | * Stelian Pop <stelian.pop@leadtechdesign.com> | |
4 | * Lead Tech Design <www.leadtechdesign.com> | |
5 | * | |
6 | * Configuation settings for the AT91SAM9263EK board. | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* ARM asynchronous clock */ | |
56a2479c | 31 | #define AT91_CPU_NAME "AT91SAM9263" |
8e429b3e SP |
32 | #define AT91_MAIN_CLOCK 199919000 /* from 16.367 MHz crystal */ |
33 | #define AT91_MASTER_CLOCK 99959500 /* peripheral = main / 2 */ | |
34 | #define CFG_HZ 1000000 /* 1us resolution */ | |
35 | ||
36 | #define AT91_SLOW_CLOCK 32768 /* slow clock */ | |
37 | ||
38 | #define CONFIG_ARM926EJS 1 /* This is an ARM926EJS Core */ | |
39 | #define CONFIG_AT91SAM9263 1 /* It's an Atmel AT91SAM9263 SoC*/ | |
40 | #define CONFIG_AT91SAM9263EK 1 /* on an AT91SAM9263EK Board */ | |
41 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
42 | ||
43 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
44 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
45 | #define CONFIG_INITRD_TAG 1 | |
46 | ||
47 | #define CONFIG_SKIP_LOWLEVEL_INIT | |
48 | #define CONFIG_SKIP_RELOCATE_UBOOT | |
49 | ||
50 | /* | |
51 | * Hardware drivers | |
52 | */ | |
53 | #define CONFIG_ATMEL_USART 1 | |
54 | #undef CONFIG_USART0 | |
55 | #undef CONFIG_USART1 | |
56 | #undef CONFIG_USART2 | |
57 | #define CONFIG_USART3 1 /* USART 3 is DBGU */ | |
58 | ||
56a2479c SP |
59 | /* LCD */ |
60 | #define CONFIG_LCD 1 | |
61 | #define LCD_BPP LCD_COLOR8 | |
62 | #define CONFIG_LCD_LOGO 1 | |
63 | #undef LCD_TEST_PATTERN | |
64 | #define CONFIG_LCD_INFO 1 | |
65 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
66 | #define CFG_WHITE_ON_BLACK 1 | |
67 | #define CONFIG_ATMEL_LCD 1 | |
68 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
69 | #define CFG_CONSOLE_IS_IN_ENV 1 | |
70 | ||
8e429b3e SP |
71 | #define CONFIG_BOOTDELAY 3 |
72 | ||
8e429b3e SP |
73 | /* |
74 | * BOOTP options | |
75 | */ | |
76 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
77 | #define CONFIG_BOOTP_BOOTPATH 1 | |
78 | #define CONFIG_BOOTP_GATEWAY 1 | |
79 | #define CONFIG_BOOTP_HOSTNAME 1 | |
80 | ||
81 | /* | |
82 | * Command line configuration. | |
83 | */ | |
84 | #include <config_cmd_default.h> | |
85 | #undef CONFIG_CMD_BDI | |
86 | #undef CONFIG_CMD_IMI | |
87 | #undef CONFIG_CMD_AUTOSCRIPT | |
88 | #undef CONFIG_CMD_FPGA | |
89 | #undef CONFIG_CMD_LOADS | |
90 | #undef CONFIG_CMD_IMLS | |
91 | ||
92 | #define CONFIG_CMD_PING 1 | |
93 | #define CONFIG_CMD_DHCP 1 | |
94 | #define CONFIG_CMD_NAND 1 | |
95 | #define CONFIG_CMD_USB 1 | |
96 | ||
97 | /* SDRAM */ | |
98 | #define CONFIG_NR_DRAM_BANKS 1 | |
99 | #define PHYS_SDRAM 0x20000000 | |
100 | #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */ | |
101 | ||
102 | /* DataFlash */ | |
103 | #define CONFIG_HAS_DATAFLASH 1 | |
104 | #define CFG_SPI_WRITE_TOUT (5*CFG_HZ) | |
105 | #define CFG_MAX_DATAFLASH_BANKS 1 | |
106 | #define CFG_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
107 | #define AT91_SPI_CLK 15000000 | |
108 | #define DATAFLASH_TCSS (0x1a << 16) | |
109 | #define DATAFLASH_TCHS (0x1 << 24) | |
110 | ||
111 | /* NOR flash, if populated */ | |
112 | #if 1 | |
113 | #define CFG_NO_FLASH 1 | |
114 | #else | |
115 | #define CFG_FLASH_CFI 1 | |
00b1883a | 116 | #define CONFIG_FLASH_CFI_DRIVER 1 |
8e429b3e SP |
117 | #define PHYS_FLASH_1 0x10000000 |
118 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
119 | #define CFG_MAX_FLASH_SECT 256 | |
120 | #define CFG_MAX_FLASH_BANKS 1 | |
121 | #endif | |
122 | ||
123 | /* NAND flash */ | |
124 | #define NAND_MAX_CHIPS 1 | |
125 | #define CFG_MAX_NAND_DEVICE 1 | |
126 | #define CFG_NAND_BASE 0x40000000 | |
127 | #define CFG_NAND_DBW_8 1 | |
128 | ||
129 | /* Ethernet */ | |
130 | #define CONFIG_MACB 1 | |
131 | #define CONFIG_RMII 1 | |
132 | #define CONFIG_NET_MULTI 1 | |
133 | #define CONFIG_NET_RETRY_COUNT 20 | |
134 | #define CONFIG_RESET_PHY_R 1 | |
135 | ||
136 | /* USB */ | |
137 | #define CONFIG_USB_OHCI_NEW 1 | |
138 | #define LITTLEENDIAN 1 | |
139 | #define CONFIG_DOS_PARTITION 1 | |
140 | #define CFG_USB_OHCI_CPU_INIT 1 | |
141 | #define CFG_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
142 | #define CFG_USB_OHCI_SLOT_NAME "at91sam9263" | |
143 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 2 | |
144 | #define CONFIG_USB_STORAGE 1 | |
145 | ||
146 | #define CFG_LOAD_ADDR 0x22000000 /* load address */ | |
147 | ||
148 | #define CFG_MEMTEST_START PHYS_SDRAM | |
149 | #define CFG_MEMTEST_END 0x23e00000 | |
150 | ||
151 | #define CFG_USE_DATAFLASH 1 | |
152 | #undef CFG_USE_NANDFLASH | |
153 | ||
154 | #ifdef CFG_USE_DATAFLASH | |
155 | ||
156 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
057c849c | 157 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 |
8e429b3e SP |
158 | #define CFG_MONITOR_BASE (CFG_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
159 | #define CFG_ENV_OFFSET 0x4200 | |
160 | #define CFG_ENV_ADDR (CFG_DATAFLASH_LOGIC_ADDR_CS0 + CFG_ENV_OFFSET) | |
161 | #define CFG_ENV_SIZE 0x4200 | |
162 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0042000 0x22000000 0x210000; bootm" | |
163 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
164 | "root=/dev/mtdblock0 " \ | |
165 | "mtdparts=at91_nand:-(root) "\ | |
166 | "rw rootfstype=jffs2" | |
167 | ||
168 | #else /* CFG_USE_NANDFLASH */ | |
169 | ||
170 | /* bootstrap + u-boot + env + linux in nandflash */ | |
51bfee19 | 171 | #define CONFIG_ENV_IS_IN_NAND 1 |
8e429b3e SP |
172 | #define CFG_ENV_OFFSET 0x60000 |
173 | #define CFG_ENV_OFFSET_REDUND 0x80000 | |
174 | #define CFG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ | |
175 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0xA0000 0x200000; bootm" | |
176 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ | |
177 | "root=/dev/mtdblock5 " \ | |
178 | "mtdparts=at91_nand:128k(bootstrap)ro,256k(uboot)ro,128k(env1)ro,128k(env2)ro,2M(linux),-(root) " \ | |
179 | "rw rootfstype=jffs2" | |
180 | ||
181 | #endif | |
182 | ||
183 | #define CONFIG_BAUDRATE 115200 | |
184 | #define CFG_BAUDRATE_TABLE {115200 , 19200, 38400, 57600, 9600 } | |
185 | ||
186 | #define CFG_PROMPT "U-Boot> " | |
187 | #define CFG_CBSIZE 256 | |
188 | #define CFG_MAXARGS 16 | |
189 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
190 | #define CFG_LONGHELP 1 | |
191 | #define CONFIG_CMDLINE_EDITING 1 | |
192 | ||
193 | #define ROUND(A, B) (((A) + (B)) & ~((B) - 1)) | |
194 | /* | |
195 | * Size of malloc() pool | |
196 | */ | |
197 | #define CFG_MALLOC_LEN ROUND(3 * CFG_ENV_SIZE + 128*1024, 0x1000) | |
198 | #define CFG_GBL_DATA_SIZE 128 /* 128 bytes for initial data */ | |
199 | ||
200 | #define CONFIG_STACKSIZE (32*1024) /* regular stack */ | |
201 | ||
202 | #ifdef CONFIG_USE_IRQ | |
203 | #error CONFIG_USE_IRQ not supported | |
204 | #endif | |
205 | ||
206 | #endif |