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8e429b3e SP |
1 | /* |
2 | * (C) Copyright 2007-2008 | |
c9e798d3 | 3 | * Stelian Pop <stelian@popies.net> |
8e429b3e SP |
4 | * Lead Tech Design <www.leadtechdesign.com> |
5 | * | |
6 | * Configuation settings for the AT91SAM9263EK board. | |
7 | * | |
1a459660 | 8 | * SPDX-License-Identifier: GPL-2.0+ |
8e429b3e SP |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
cd46b0f2 XH |
14 | /* |
15 | * SoC must be defined first, before hardware.h is included. | |
16 | * In this case SoC is defined in boards.cfg. | |
17 | */ | |
18 | #include <asm/hardware.h> | |
19 | ||
5e7d0917 | 20 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
cd46b0f2 | 21 | #define CONFIG_SYS_TEXT_BASE 0x21F00000 |
5e7d0917 | 22 | #else |
23 | #define CONFIG_SYS_TEXT_BASE 0x0000000 | |
24 | #endif | |
cd46b0f2 | 25 | |
8e429b3e | 26 | /* ARM asynchronous clock */ |
cd46b0f2 XH |
27 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16367660 /* 16.367 MHz crystal */ |
28 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 | |
cd46b0f2 XH |
29 | |
30 | #define CONFIG_AT91SAM9263EK 1 /* It's an AT91SAM9263EK Board */ | |
8e429b3e | 31 | |
dc39ae95 | 32 | #define CONFIG_ARCH_CPU_INIT |
8e429b3e SP |
33 | |
34 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ | |
35 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
36 | #define CONFIG_INITRD_TAG 1 | |
37 | ||
1b3b7c64 | 38 | #ifndef CONFIG_SYS_USE_BOOT_NORFLASH |
8e429b3e | 39 | #define CONFIG_SKIP_LOWLEVEL_INIT |
cd46b0f2 XH |
40 | #else |
41 | #define CONFIG_SYS_USE_NORFLASH | |
1b3b7c64 | 42 | #endif |
8e429b3e SP |
43 | |
44 | /* | |
45 | * Hardware drivers | |
46 | */ | |
cd46b0f2 XH |
47 | #define CONFIG_ATMEL_LEGACY |
48 | #define CONFIG_AT91_GPIO 1 | |
49 | #define CONFIG_AT91_GPIO_PULLUP 1 | |
50 | ||
51 | /* serial console */ | |
52 | #define CONFIG_ATMEL_USART | |
53 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
54 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
55 | #define CONFIG_BAUDRATE 115200 | |
8e429b3e | 56 | |
56a2479c | 57 | /* LCD */ |
56a2479c SP |
58 | #define LCD_BPP LCD_COLOR8 |
59 | #define CONFIG_LCD_LOGO 1 | |
60 | #undef LCD_TEST_PATTERN | |
61 | #define CONFIG_LCD_INFO 1 | |
62 | #define CONFIG_LCD_INFO_BELOW_LOGO 1 | |
cd46b0f2 | 63 | #define CONFIG_SYS_WHITE_ON_BLACK 1 |
56a2479c SP |
64 | #define CONFIG_ATMEL_LCD 1 |
65 | #define CONFIG_ATMEL_LCD_BGR555 1 | |
56a2479c | 66 | |
a484b00b JCPV |
67 | /* LED */ |
68 | #define CONFIG_AT91_LED | |
cd46b0f2 XH |
69 | #define CONFIG_RED_LED AT91_PIN_PB7 /* the power led */ |
70 | #define CONFIG_GREEN_LED AT91_PIN_PB8 /* the user1 led */ | |
71 | #define CONFIG_YELLOW_LED AT91_PIN_PC29 /* the user2 led */ | |
a484b00b | 72 | |
8e429b3e | 73 | |
8e429b3e SP |
74 | /* |
75 | * BOOTP options | |
76 | */ | |
77 | #define CONFIG_BOOTP_BOOTFILESIZE 1 | |
78 | #define CONFIG_BOOTP_BOOTPATH 1 | |
79 | #define CONFIG_BOOTP_GATEWAY 1 | |
80 | #define CONFIG_BOOTP_HOSTNAME 1 | |
81 | ||
82 | /* | |
83 | * Command line configuration. | |
84 | */ | |
8e429b3e | 85 | #define CONFIG_CMD_NAND 1 |
8e429b3e SP |
86 | |
87 | /* SDRAM */ | |
88 | #define CONFIG_NR_DRAM_BANKS 1 | |
cd46b0f2 XH |
89 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
90 | #define CONFIG_SYS_SDRAM_SIZE 0x04000000 | |
91 | ||
92 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
93 | (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
8e429b3e SP |
94 | |
95 | /* DataFlash */ | |
4758ebdd | 96 | #define CONFIG_ATMEL_DATAFLASH_SPI |
8e429b3e | 97 | #define CONFIG_HAS_DATAFLASH 1 |
6d0f6bcf JCPV |
98 | #define CONFIG_SYS_MAX_DATAFLASH_BANKS 1 |
99 | #define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 0xC0000000 /* CS0 */ | |
8e429b3e SP |
100 | #define AT91_SPI_CLK 15000000 |
101 | #define DATAFLASH_TCSS (0x1a << 16) | |
102 | #define DATAFLASH_TCHS (0x1 << 24) | |
103 | ||
81724e09 AH |
104 | /* MMC */ |
105 | #ifdef CONFIG_CMD_MMC | |
81724e09 AH |
106 | #define CONFIG_GENERIC_ATMEL_MCI |
107 | #endif | |
108 | ||
8e429b3e | 109 | /* NOR flash, if populated */ |
1b3b7c64 | 110 | #ifdef CONFIG_SYS_USE_NORFLASH |
6d0f6bcf | 111 | #define CONFIG_SYS_FLASH_CFI 1 |
1b3b7c64 JCPV |
112 | #define CONFIG_FLASH_CFI_DRIVER 1 |
113 | #define PHYS_FLASH_1 0x10000000 | |
6d0f6bcf JCPV |
114 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
115 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
116 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
1b3b7c64 JCPV |
117 | |
118 | #define CONFIG_SYS_MONITOR_SEC 1:0-3 | |
119 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
120 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
121 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
5e7d0917 | 122 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x007E0000) |
1b3b7c64 JCPV |
123 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SIZE) |
124 | ||
125 | /* Address and size of Primary Environment Sector */ | |
5e7d0917 | 126 | #define CONFIG_ENV_SIZE 0x10000 |
1b3b7c64 | 127 | |
1b3b7c64 | 128 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
93ea89f0 | 129 | "monitor_base=" __stringify(CONFIG_SYS_MONITOR_BASE) "\0" \ |
1b3b7c64 JCPV |
130 | "update=" \ |
131 | "protect off ${monitor_base} +${filesize};" \ | |
132 | "erase ${monitor_base} +${filesize};" \ | |
88461f16 | 133 | "cp.b ${fileaddr} ${monitor_base} ${filesize};" \ |
1b3b7c64 JCPV |
134 | "protect on ${monitor_base} +${filesize}\0" |
135 | ||
136 | #ifndef CONFIG_SKIP_LOWLEVEL_INIT | |
137 | #define MASTER_PLL_MUL 171 | |
138 | #define MASTER_PLL_DIV 14 | |
1b34f00c | 139 | #define MASTER_PLL_OUT 3 |
1b3b7c64 JCPV |
140 | |
141 | /* clocks */ | |
142 | #define CONFIG_SYS_MOR_VAL \ | |
1b34f00c JS |
143 | (AT91_PMC_MOR_MOSCEN | AT91_PMC_MOR_OSCOUNT(255)) |
144 | #define CONFIG_SYS_PLLAR_VAL \ | |
145 | (AT91_PMC_PLLAR_29 | \ | |
146 | AT91_PMC_PLLXR_OUT(MASTER_PLL_OUT) | \ | |
147 | AT91_PMC_PLLXR_PLLCOUNT(63) | \ | |
148 | AT91_PMC_PLLXR_MUL(MASTER_PLL_MUL - 1) | \ | |
149 | AT91_PMC_PLLXR_DIV(MASTER_PLL_DIV)) | |
1b3b7c64 JCPV |
150 | |
151 | /* PCK/2 = MCK Master Clock from PLLA */ | |
152 | #define CONFIG_SYS_MCKR1_VAL \ | |
1b34f00c JS |
153 | (AT91_PMC_MCKR_CSS_SLOW | AT91_PMC_MCKR_PRES_1 | \ |
154 | AT91_PMC_MCKR_MDIV_2) | |
155 | ||
1b3b7c64 JCPV |
156 | /* PCK/2 = MCK Master Clock from PLLA */ |
157 | #define CONFIG_SYS_MCKR2_VAL \ | |
1b34f00c JS |
158 | (AT91_PMC_MCKR_CSS_PLLA | AT91_PMC_MCKR_PRES_1 | \ |
159 | AT91_PMC_MCKR_MDIV_2) | |
1b3b7c64 JCPV |
160 | |
161 | /* define PDC[31:16] as DATA[31:16] */ | |
162 | #define CONFIG_SYS_PIOD_PDR_VAL1 0xFFFF0000 | |
163 | /* no pull-up for D[31:16] */ | |
164 | #define CONFIG_SYS_PIOD_PPUDR_VAL 0xFFFF0000 | |
165 | /* EBI0_CSA, CS1 SDRAM, CS3 NAND Flash, 3.3V memories */ | |
1b34f00c JS |
166 | #define CONFIG_SYS_MATRIX_EBICSA_VAL \ |
167 | (AT91_MATRIX_CSA_DBPUC | AT91_MATRIX_CSA_VDDIOMSEL_3_3V | \ | |
168 | AT91_MATRIX_CSA_EBI_CS1A) | |
1b3b7c64 JCPV |
169 | |
170 | /* SDRAM */ | |
171 | /* SDRAMC_MR Mode register */ | |
172 | #define CONFIG_SYS_SDRC_MR_VAL1 0 | |
173 | /* SDRAMC_TR - Refresh Timer register */ | |
174 | #define CONFIG_SYS_SDRC_TR_VAL1 0x13C | |
175 | /* SDRAMC_CR - Configuration register*/ | |
176 | #define CONFIG_SYS_SDRC_CR_VAL \ | |
177 | (AT91_SDRAMC_NC_9 | \ | |
178 | AT91_SDRAMC_NR_13 | \ | |
179 | AT91_SDRAMC_NB_4 | \ | |
180 | AT91_SDRAMC_CAS_3 | \ | |
181 | AT91_SDRAMC_DBW_32 | \ | |
182 | (1 << 8) | /* Write Recovery Delay */ \ | |
183 | (7 << 12) | /* Row Cycle Delay */ \ | |
184 | (2 << 16) | /* Row Precharge Delay */ \ | |
185 | (2 << 20) | /* Row to Column Delay */ \ | |
186 | (5 << 24) | /* Active to Precharge Delay */ \ | |
187 | (1 << 28)) /* Exit Self Refresh to Active Delay */ | |
188 | ||
189 | /* Memory Device Register -> SDRAM */ | |
190 | #define CONFIG_SYS_SDRC_MDR_VAL AT91_SDRAMC_MD_SDRAM | |
191 | #define CONFIG_SYS_SDRC_MR_VAL2 AT91_SDRAMC_MODE_PRECHARGE | |
192 | #define CONFIG_SYS_SDRAM_VAL1 0 /* SDRAM_BASE */ | |
193 | #define CONFIG_SYS_SDRC_MR_VAL3 AT91_SDRAMC_MODE_REFRESH | |
194 | #define CONFIG_SYS_SDRAM_VAL2 0 /* SDRAM_BASE */ | |
195 | #define CONFIG_SYS_SDRAM_VAL3 0 /* SDRAM_BASE */ | |
196 | #define CONFIG_SYS_SDRAM_VAL4 0 /* SDRAM_BASE */ | |
197 | #define CONFIG_SYS_SDRAM_VAL5 0 /* SDRAM_BASE */ | |
198 | #define CONFIG_SYS_SDRAM_VAL6 0 /* SDRAM_BASE */ | |
199 | #define CONFIG_SYS_SDRAM_VAL7 0 /* SDRAM_BASE */ | |
200 | #define CONFIG_SYS_SDRAM_VAL8 0 /* SDRAM_BASE */ | |
201 | #define CONFIG_SYS_SDRAM_VAL9 0 /* SDRAM_BASE */ | |
202 | #define CONFIG_SYS_SDRC_MR_VAL4 AT91_SDRAMC_MODE_LMR | |
203 | #define CONFIG_SYS_SDRAM_VAL10 0 /* SDRAM_BASE */ | |
204 | #define CONFIG_SYS_SDRC_MR_VAL5 AT91_SDRAMC_MODE_NORMAL | |
205 | #define CONFIG_SYS_SDRAM_VAL11 0 /* SDRAM_BASE */ | |
206 | #define CONFIG_SYS_SDRC_TR_VAL2 1200 /* SDRAM_TR */ | |
207 | #define CONFIG_SYS_SDRAM_VAL12 0 /* SDRAM_BASE */ | |
208 | ||
209 | /* setup SMC0, CS0 (NOR Flash) - 16-bit, 15 WS */ | |
1b34f00c JS |
210 | #define CONFIG_SYS_SMC0_SETUP0_VAL \ |
211 | (AT91_SMC_SETUP_NWE(10) | AT91_SMC_SETUP_NCS_WR(10) | \ | |
212 | AT91_SMC_SETUP_NRD(10) | AT91_SMC_SETUP_NCS_RD(10)) | |
213 | #define CONFIG_SYS_SMC0_PULSE0_VAL \ | |
214 | (AT91_SMC_PULSE_NWE(11) | AT91_SMC_PULSE_NCS_WR(11) | \ | |
215 | AT91_SMC_PULSE_NRD(11) | AT91_SMC_PULSE_NCS_RD(11)) | |
1b3b7c64 | 216 | #define CONFIG_SYS_SMC0_CYCLE0_VAL \ |
1b34f00c | 217 | (AT91_SMC_CYCLE_NWE(22) | AT91_SMC_CYCLE_NRD(22)) |
1b3b7c64 | 218 | #define CONFIG_SYS_SMC0_MODE0_VAL \ |
1b34f00c JS |
219 | (AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE | \ |
220 | AT91_SMC_MODE_DBW_16 | \ | |
221 | AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(6)) | |
1b3b7c64 JCPV |
222 | |
223 | /* user reset enable */ | |
224 | #define CONFIG_SYS_RSTC_RMR_VAL \ | |
225 | (AT91_RSTC_KEY | \ | |
1b34f00c JS |
226 | AT91_RSTC_MR_URSTEN | \ |
227 | AT91_RSTC_MR_ERSTL(15)) | |
1b3b7c64 JCPV |
228 | |
229 | /* Disable Watchdog */ | |
230 | #define CONFIG_SYS_WDTC_WDMR_VAL \ | |
1b34f00c JS |
231 | (AT91_WDT_MR_WDIDLEHLT | AT91_WDT_MR_WDDBGHLT | \ |
232 | AT91_WDT_MR_WDV(0xfff) | \ | |
233 | AT91_WDT_MR_WDDIS | \ | |
234 | AT91_WDT_MR_WDD(0xfff)) | |
235 | ||
1b3b7c64 | 236 | #endif |
8e429b3e SP |
237 | #endif |
238 | ||
239 | /* NAND flash */ | |
74c076d6 JCPV |
240 | #ifdef CONFIG_CMD_NAND |
241 | #define CONFIG_NAND_ATMEL | |
6d0f6bcf | 242 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
cd46b0f2 | 243 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
6d0f6bcf | 244 | #define CONFIG_SYS_NAND_DBW_8 1 |
74c076d6 JCPV |
245 | /* our ALE is AD21 */ |
246 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
247 | /* our CLE is AD22 */ | |
248 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
cd46b0f2 XH |
249 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD15 |
250 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PA22 | |
74c076d6 | 251 | #endif |
8e429b3e SP |
252 | |
253 | /* Ethernet */ | |
254 | #define CONFIG_MACB 1 | |
255 | #define CONFIG_RMII 1 | |
8e429b3e SP |
256 | #define CONFIG_NET_RETRY_COUNT 20 |
257 | #define CONFIG_RESET_PHY_R 1 | |
4535a24c | 258 | #define CONFIG_AT91_WANTS_COMMON_PHY |
8e429b3e SP |
259 | |
260 | /* USB */ | |
2b7178af | 261 | #define CONFIG_USB_ATMEL |
dcd2f1a0 | 262 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
8e429b3e | 263 | #define CONFIG_USB_OHCI_NEW 1 |
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 |
265 | #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00a00000 /* AT91SAM9263_UHP_BASE */ | |
266 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9263" | |
267 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
8e429b3e | 268 | |
6d0f6bcf | 269 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
8e429b3e | 270 | |
cd46b0f2 | 271 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
6d0f6bcf | 272 | #define CONFIG_SYS_MEMTEST_END 0x23e00000 |
8e429b3e | 273 | |
6d0f6bcf | 274 | #ifdef CONFIG_SYS_USE_DATAFLASH |
8e429b3e SP |
275 | |
276 | /* bootstrap + u-boot + env + linux in dataflash on CS0 */ | |
057c849c | 277 | #define CONFIG_ENV_IS_IN_DATAFLASH 1 |
6d0f6bcf | 278 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + 0x8400) |
0e8d1586 | 279 | #define CONFIG_ENV_OFFSET 0x4200 |
6d0f6bcf | 280 | #define CONFIG_ENV_ADDR (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET) |
0e8d1586 | 281 | #define CONFIG_ENV_SIZE 0x4200 |
e139cb31 | 282 | #define CONFIG_BOOTCOMMAND "cp.b 0xC0084000 0x22000000 0x210000; bootm" |
8e429b3e SP |
283 | #define CONFIG_BOOTARGS "console=ttyS0,115200 " \ |
284 | "root=/dev/mtdblock0 " \ | |
918319c7 | 285 | "mtdparts=atmel_nand:-(root) "\ |
8e429b3e SP |
286 | "rw rootfstype=jffs2" |
287 | ||
1b3b7c64 | 288 | #elif CONFIG_SYS_USE_NANDFLASH |
8e429b3e SP |
289 | |
290 | /* bootstrap + u-boot + env + linux in nandflash */ | |
cd46b0f2 | 291 | #define CONFIG_ENV_IS_IN_NAND 1 |
0c58cfa9 BS |
292 | #define CONFIG_ENV_OFFSET 0xc0000 |
293 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 | |
0e8d1586 | 294 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
0c58cfa9 BS |
295 | #define CONFIG_BOOTCOMMAND "nand read 0x22000000 0x200000 0x300000; bootm" |
296 | #define CONFIG_BOOTARGS \ | |
297 | "console=ttyS0,115200 earlyprintk " \ | |
298 | "mtdparts=atmel_nand:256k(bootstrap)ro,512k(uboot)ro," \ | |
299 | "256k(env),256k(env_redundant),256k(spare)," \ | |
300 | "512k(dtb),6M(kernel)ro,-(rootfs) " \ | |
301 | "root=/dev/mtdblock7 rw rootfstype=jffs2" | |
8e429b3e SP |
302 | #endif |
303 | ||
6d0f6bcf JCPV |
304 | #define CONFIG_SYS_CBSIZE 256 |
305 | #define CONFIG_SYS_MAXARGS 16 | |
6d0f6bcf | 306 | #define CONFIG_SYS_LONGHELP 1 |
cd46b0f2 | 307 | #define CONFIG_CMDLINE_EDITING 1 |
03bab009 | 308 | #define CONFIG_AUTO_COMPLETE |
8e429b3e | 309 | |
8e429b3e SP |
310 | /* |
311 | * Size of malloc() pool | |
312 | */ | |
cd46b0f2 | 313 | #define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000) |
8e429b3e | 314 | |
8e429b3e | 315 | #endif |