[people/ms/u-boot.git] / include / configs / at91sam9m10g45ek.h

/*
 * (C) Copyright 2007-2008
 * Stelian Pop <stelian@popies.net>
 * Lead Tech Design <www.leadtechdesign.com>
 *
 * Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_SLOW_CLOCK      32768
#define CONFIG_SYS_AT91_MAIN_CLOCK      12000000 /* from 12 MHz crystal */

#define CONFIG_AT91SAM9M10G45EK

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* general purpose I/O */
#define CONFIG_ATMEL_LEGACY		/* required until (g)pio is fixed */

/* LCD */
#define LCD_BPP				LCD_COLOR8
#define CONFIG_LCD_LOGO
#undef LCD_TEST_PATTERN
#define CONFIG_LCD_INFO
#define CONFIG_LCD_INFO_BELOW_LOGO
#define CONFIG_ATMEL_LCD
#define CONFIG_ATMEL_LCD_RGB565
/* board specific(not enough SRAM) */
#define CONFIG_AT91SAM9G45_LCD_BASE		0x73E00000

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE           0x70000000
#define CONFIG_SYS_SDRAM_SIZE		0x08000000

#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)

/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE		1
#define CONFIG_SYS_NAND_BASE			ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
/* our ALE is AD21 */
#define CONFIG_SYS_NAND_MASK_ALE		(1 << 21)
/* our CLE is AD22 */
#define CONFIG_SYS_NAND_MASK_CLE		(1 << 22)
#define CONFIG_SYS_NAND_ENABLE_PIN		AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN		AT91_PIN_PC8

#endif

/* Ethernet */
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY

#define CONFIG_SYS_LOAD_ADDR		0x22000000	/* load address */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		0x23e00000

#ifdef CONFIG_NAND_BOOT
/* bootstrap + u-boot + env in nandflash */
#define CONFIG_ENV_OFFSET		0x120000
#define CONFIG_ENV_OFFSET_REDUND	0x100000
#define CONFIG_ENV_SIZE			0x20000

#define CONFIG_BOOTCOMMAND						\
	"nand read 0x70000000 0x200000 0x300000;"			\
	"bootm 0x70000000"
#elif CONFIG_SD_BOOT
/* bootstrap + u-boot + env + linux in mmc */
#define CONFIG_ENV_SIZE		0x4000

#define CONFIG_BOOTCOMMAND	"fatload mmc 0:1 0x71000000 dtb; " \
				"fatload mmc 0:1 0x72000000 zImage; " \
				"bootz 0x72000000 - 0x71000000"
#endif

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x300000
#define CONFIG_SPL_MAX_SIZE		0x010000
#define CONFIG_SPL_STACK		0x310000

#define CONFIG_SYS_MONITOR_LEN		0x80000

#ifdef CONFIG_SD_BOOT

#define CONFIG_SPL_BSS_START_ADDR	0x70000000
#define CONFIG_SPL_BSS_MAX_SIZE		0x00080000
#define CONFIG_SYS_SPL_MALLOC_START	0x70080000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000

#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot.img"

#elif CONFIG_NAND_BOOT
#define CONFIG_SPL_NAND_DRIVERS
#define CONFIG_SPL_NAND_BASE
#define CONFIG_SPL_NAND_ECC
#define CONFIG_SPL_NAND_SOFTECC
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#define CONFIG_SYS_NAND_U_BOOT_SIZE	0x80000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE

#define CONFIG_SYS_NAND_PAGE_SIZE	0x800
#define CONFIG_SYS_NAND_BLOCK_SIZE	0x20000
#define CONFIG_SYS_NAND_PAGE_COUNT	64
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCSIZE		256
#define CONFIG_SYS_NAND_ECCBYTES	3
#define CONFIG_SYS_NAND_OOBSIZE		64
#define CONFIG_SYS_NAND_ECCPOS		{ 40, 41, 42, 43, 44, 45, 46, 47, \
					  48, 49, 50, 51, 52, 53, 54, 55, \
					  56, 57, 58, 59, 60, 61, 62, 63, }
#endif

#define CONFIG_SPL_ATMEL_SIZE
#define CONFIG_SYS_MASTER_CLOCK		132096000
#define CONFIG_SYS_AT91_PLLA		0x20c73f03
#define CONFIG_SYS_MCKR			0x1301
#define CONFIG_SYS_MCKR_CSS		0x1302

#endif
Commit	Line	Data
22ee6473 SG	1	/*
22ee6473 SG	2	* (C) Copyright 2007-2008
c9e798d3	3	* Stelian Pop <stelian@popies.net>
22ee6473 SG	4	* Lead Tech Design <www.leadtechdesign.com>
	5	*
	6	* Configuation settings for the AT91SAM9M10G45EK board(and AT91SAM9G45EKES).
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
22ee6473 SG	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
5cfeec51	14	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
425de62d	15
22ee6473	16	/* ARM asynchronous clock */
5cfeec51 TP	17	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
5cfeec51 TP	18	#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
5cfeec51 TP	19
5cfeec51 TP	20	#define CONFIG_AT91SAM9M10G45EK
22ee6473	21
5cfeec51 TP	22	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	23	#define CONFIG_SETUP_MEMORY_TAGS
	24	#define CONFIG_INITRD_TAG
22ee6473	25	#define CONFIG_SKIP_LOWLEVEL_INIT
5cfeec51 TP	26
	27	/* general purpose I/O */
	28	#define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */
5cfeec51	29
22ee6473	30	/* LCD */
22ee6473	31	#define LCD_BPP LCD_COLOR8
5cfeec51	32	#define CONFIG_LCD_LOGO
22ee6473	33	#undef LCD_TEST_PATTERN
5cfeec51 TP	34	#define CONFIG_LCD_INFO
5cfeec51 TP	35	#define CONFIG_LCD_INFO_BELOW_LOGO
5cfeec51 TP	36	#define CONFIG_ATMEL_LCD
5cfeec51 TP	37	#define CONFIG_ATMEL_LCD_RGB565
22ee6473 SG	38	/* board specific(not enough SRAM) */
	39	#define CONFIG_AT91SAM9G45_LCD_BASE 0x73E00000
	40
22ee6473 SG	41	/*
	42	* BOOTP options
	43	*/
5cfeec51	44	#define CONFIG_BOOTP_BOOTFILESIZE
22ee6473	45
22ee6473 SG	46	/* SDRAM */
22ee6473 SG	47	#define CONFIG_NR_DRAM_BANKS 1
e61ed48f	48	#define CONFIG_SYS_SDRAM_BASE 0x70000000
5cfeec51	49	#define CONFIG_SYS_SDRAM_SIZE 0x08000000
22ee6473	50
5cfeec51	51	#define CONFIG_SYS_INIT_SP_ADDR \
59b37122	52	(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
5cfeec51	53
22ee6473 SG	54	/* NAND flash */
22ee6473 SG	55	#ifdef CONFIG_CMD_NAND
22ee6473 SG	56	#define CONFIG_NAND_ATMEL
22ee6473 SG	57	#define CONFIG_SYS_MAX_NAND_DEVICE 1
5cfeec51 TP	58	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
5cfeec51 TP	59	#define CONFIG_SYS_NAND_DBW_8
22ee6473 SG	60	/* our ALE is AD21 */
	61	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
	62	/* our CLE is AD22 */
	63	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
	64	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	65	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC8
2eb99ca8	66
22ee6473 SG	67	#endif
	68
	69	/* Ethernet */
5cfeec51	70	#define CONFIG_RESET_PHY_R
4535a24c	71	#define CONFIG_AT91_WANTS_COMMON_PHY
22ee6473	72
5cfeec51	73	#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
22ee6473	74
5cfeec51 TP	75	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
5cfeec51 TP	76	#define CONFIG_SYS_MEMTEST_END 0x23e00000
22ee6473	77
5541543f	78	#ifdef CONFIG_NAND_BOOT
5cfeec51	79	/* bootstrap + u-boot + env in nandflash */
59b37122	80	#define CONFIG_ENV_OFFSET 0x120000
0c58cfa9	81	#define CONFIG_ENV_OFFSET_REDUND 0x100000
5cfeec51 TP	82	#define CONFIG_ENV_SIZE 0x20000
5cfeec51 TP	83
0c58cfa9 BS	84	#define CONFIG_BOOTCOMMAND \
0c58cfa9 BS	85	"nand read 0x70000000 0x200000 0x300000;" \
5cfeec51	86	"bootm 0x70000000"
5541543f	87	#elif CONFIG_SD_BOOT
9637a1bb	88	/* bootstrap + u-boot + env + linux in mmc */
9637a1bb WJ	89	#define CONFIG_ENV_SIZE 0x4000
9637a1bb WJ	90
9637a1bb WJ	91	#define CONFIG_BOOTCOMMAND "fatload mmc 0:1 0x71000000 dtb; " \
	92	"fatload mmc 0:1 0x72000000 zImage; " \
	93	"bootz 0x72000000 - 0x71000000"
	94	#endif
5cfeec51	95
22ee6473 SG	96	/*
	97	* Size of malloc() pool
	98	*/
	99	#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024, 0x1000)
22ee6473	100
41d41a93	101	/* Defines for SPL */
41d41a93 BS	102	#define CONFIG_SPL_TEXT_BASE 0x300000
	103	#define CONFIG_SPL_MAX_SIZE 0x010000
	104	#define CONFIG_SPL_STACK 0x310000
	105
41d41a93 BS	106	#define CONFIG_SYS_MONITOR_LEN 0x80000
41d41a93 BS	107
5541543f	108	#ifdef CONFIG_SD_BOOT
41d41a93 BS	109
	110	#define CONFIG_SPL_BSS_START_ADDR 0x70000000
	111	#define CONFIG_SPL_BSS_MAX_SIZE 0x00080000
	112	#define CONFIG_SYS_SPL_MALLOC_START 0x70080000
	113	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000
	114
41d41a93 BS	115	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
41d41a93 BS	116	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
41d41a93	117
5541543f	118	#elif CONFIG_NAND_BOOT
41d41a93 BS	119	#define CONFIG_SPL_NAND_DRIVERS
	120	#define CONFIG_SPL_NAND_BASE
	121	#define CONFIG_SPL_NAND_ECC
	122	#define CONFIG_SPL_NAND_SOFTECC
	123	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	124	#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000
	125	#define CONFIG_SYS_NAND_5_ADDR_CYCLE
	126
	127	#define CONFIG_SYS_NAND_PAGE_SIZE 0x800
	128	#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
	129	#define CONFIG_SYS_NAND_PAGE_COUNT 64
	130	#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
	131	#define CONFIG_SYS_NAND_ECCSIZE 256
	132	#define CONFIG_SYS_NAND_ECCBYTES 3
	133	#define CONFIG_SYS_NAND_OOBSIZE 64
	134	#define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \
	135	48, 49, 50, 51, 52, 53, 54, 55, \
	136	56, 57, 58, 59, 60, 61, 62, 63, }
	137	#endif
	138
	139	#define CONFIG_SPL_ATMEL_SIZE
	140	#define CONFIG_SYS_MASTER_CLOCK 132096000
	141	#define CONFIG_SYS_AT91_PLLA 0x20c73f03
	142	#define CONFIG_SYS_MCKR 0x1301
	143	#define CONFIG_SYS_MCKR_CSS 0x1302
	144
22ee6473	145	#endif