[people/ms/u-boot.git] / include / configs / atngw100.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * Configuration settings for the AVR32 Network Gateway
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/memory-map.h>

#define CONFIG_AVR32			1
#define CONFIG_AT32AP			1
#define CONFIG_AT32AP7000		1
#define CONFIG_ATNGW100			1

#define CFG_HZ				1000

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
 * and the PBA bus to run at 1/4 the PLL frequency.
 */
#define CONFIG_PLL			1
#define CFG_POWER_MANAGER		1
#define CFG_OSC0_HZ			20000000
#define CFG_PLL0_DIV			1
#define CFG_PLL0_MUL			7
#define CFG_PLL0_SUPPRESS_CYCLES	16
#define CFG_CLKDIV_CPU			0
#define CFG_CLKDIV_HSB			1
#define CFG_CLKDIV_PBA			2
#define CFG_CLKDIV_PBB			1

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CFG_PLL0_OPT			0x04

#define CONFIG_USART1			1

/* User serviceable stuff */
#define CONFIG_DOS_PARTITION		1

#define CONFIG_CMDLINE_TAG		1
#define CONFIG_SETUP_MEMORY_TAGS	1
#define CONFIG_INITRD_TAG		1

#define CONFIG_STACKSIZE		(2048)

#define CONFIG_BAUDRATE			115200
#define CONFIG_BOOTARGS							\
	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND						\
	"fsload; bootm"

/*
 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
 * data on the serial line may interrupt the boot sequence.
 */
#define CONFIG_BOOTDELAY		1
#define CONFIG_AUTOBOOT			1
#define CONFIG_AUTOBOOT_KEYED		1
#define CONFIG_AUTOBOOT_PROMPT				\
	"Press SPACE to abort autoboot in %d seconds\n"
#define CONFIG_AUTOBOOT_DELAY_STR	"d"
#define CONFIG_AUTOBOOT_STOP_STR	" "

/*
 * After booting the board for the first time, new ethernet addresses
 * should be generated and assigned to the environment variables
 * "ethaddr" and "eth1addr". This is normally done during production.
 */
#define CONFIG_OVERWRITE_ETHADDR_ONCE	1
#define CONFIG_NET_MULTI		1

/*
 * BOOTP/DHCP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY

#define CONFIG_DOS_PARTITION		1

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_MMC

#undef CONFIG_CMD_AUTOSCRIPT
#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_SETGETDCR
#undef CONFIG_CMD_XIMG

#define CONFIG_ATMEL_USART		1
#define CONFIG_MACB			1
#define CONFIG_PIO2			1
#define CFG_NR_PIOS			5
#define CFG_HSDRAMC			1
#define CONFIG_MMC			1

#define CFG_DCACHE_LINESZ		32
#define CFG_ICACHE_LINESZ		32

#define CONFIG_NR_DRAM_BANKS		1

#define CFG_FLASH_CFI			1
#define CFG_FLASH_CFI_DRIVER		1

#define CFG_FLASH_BASE			0x00000000
#define CFG_FLASH_SIZE			0x800000
#define CFG_MAX_FLASH_BANKS		1
#define CFG_MAX_FLASH_SECT		135

#define CFG_MONITOR_BASE		CFG_FLASH_BASE

#define CFG_INTRAM_BASE			INTERNAL_SRAM_BASE
#define CFG_INTRAM_SIZE			INTERNAL_SRAM_SIZE
#define CFG_SDRAM_BASE			EBI_SDRAM_BASE

#define CFG_ENV_IS_IN_FLASH		1
#define CFG_ENV_SIZE			65536
#define CFG_ENV_ADDR			(CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)

#define CFG_INIT_SP_ADDR		(CFG_INTRAM_BASE + CFG_INTRAM_SIZE)

#define CFG_MALLOC_LEN			(256*1024)
#define CFG_DMA_ALLOC_LEN		(16384)

/* Allow 4MB for the kernel run-time image */
#define CFG_LOAD_ADDR			(EBI_SDRAM_BASE + 0x00400000)
#define CFG_BOOTPARAMS_LEN		(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CFG_PROMPT			"U-Boot> "
#define CFG_CBSIZE			256
#define CFG_MAXARGS			16
#define CFG_PBSIZE			(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
#define CFG_LONGHELP			1

#define CFG_MEMTEST_START		EBI_SDRAM_BASE
#define CFG_MEMTEST_END			(CFG_MEMTEST_START + 0x1f00000)

#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }

#endif /* __CONFIG_H */
Commit	Line	Data
6b443944 HS	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
	4	* Configuration settings for the AVR32 Network Gateway
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24	#ifndef __CONFIG_H
	25	#define __CONFIG_H
	26
a23e277c HS	27	#include <asm/arch/memory-map.h>
a23e277c HS	28
6b443944 HS	29	#define CONFIG_AVR32 1
	30	#define CONFIG_AT32AP 1
	31	#define CONFIG_AT32AP7000 1
	32	#define CONFIG_ATNGW100 1
	33
	34	#define CFG_HZ 1000
	35
	36	/*
	37	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	38	* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
	39	* and the PBA bus to run at 1/4 the PLL frequency.
	40	*/
	41	#define CONFIG_PLL 1
	42	#define CFG_POWER_MANAGER 1
	43	#define CFG_OSC0_HZ 20000000
	44	#define CFG_PLL0_DIV 1
	45	#define CFG_PLL0_MUL 7
	46	#define CFG_PLL0_SUPPRESS_CYCLES 16
	47	#define CFG_CLKDIV_CPU 0
	48	#define CFG_CLKDIV_HSB 1
	49	#define CFG_CLKDIV_PBA 2
	50	#define CFG_CLKDIV_PBB 1
	51
	52	/*
	53	* The PLLOPT register controls the PLL like this:
	54	* icp = PLLOPT<2>
	55	* ivco = PLLOPT<1:0>
	56	*
	57	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	58	*/
	59	#define CFG_PLL0_OPT 0x04
	60
	61	#define CONFIG_USART1 1
	62
	63	/* User serviceable stuff */
	64	#define CONFIG_DOS_PARTITION 1
	65
	66	#define CONFIG_CMDLINE_TAG 1
	67	#define CONFIG_SETUP_MEMORY_TAGS 1
	68	#define CONFIG_INITRD_TAG 1
	69
	70	#define CONFIG_STACKSIZE (2048)
	71
	72	#define CONFIG_BAUDRATE 115200
	73	#define CONFIG_BOOTARGS \
	74	"console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
	75	#define CONFIG_BOOTCOMMAND \
	76	"fsload; bootm"
	77
	78	/*
	79	* Only interrupt autoboot if <space> is pressed. Otherwise, garbage
	80	* data on the serial line may interrupt the boot sequence.
	81	*/
	82	#define CONFIG_BOOTDELAY 1
	83	#define CONFIG_AUTOBOOT 1
	84	#define CONFIG_AUTOBOOT_KEYED 1
	85	#define CONFIG_AUTOBOOT_PROMPT \
33dac03b	86	"Press SPACE to abort autoboot in %d seconds\n"
6b443944 HS	87	#define CONFIG_AUTOBOOT_DELAY_STR "d"
	88	#define CONFIG_AUTOBOOT_STOP_STR " "
	89
	90	/*
	91	* After booting the board for the first time, new ethernet addresses
	92	* should be generated and assigned to the environment variables
	93	* "ethaddr" and "eth1addr". This is normally done during production.
	94	*/
	95	#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
	96	#define CONFIG_NET_MULTI 1
	97
	98	/*
	99	* BOOTP/DHCP options
	100	*/
	101	#define CONFIG_BOOTP_SUBNETMASK
	102	#define CONFIG_BOOTP_GATEWAY
	103
	104	#define CONFIG_DOS_PARTITION 1
	105
	106	/*
	107	* Command line configuration.
	108	*/
	109	#include <config_cmd_default.h>
	110
	111	#define CONFIG_CMD_ASKENV
	112	#define CONFIG_CMD_DHCP
	113	#define CONFIG_CMD_EXT2
	114	#define CONFIG_CMD_FAT
	115	#define CONFIG_CMD_JFFS2
	116	#define CONFIG_CMD_MMC
55ac7a74 DB	117
55ac7a74 DB	118	#undef CONFIG_CMD_AUTOSCRIPT
6b443944 HS	119	#undef CONFIG_CMD_FPGA
6b443944 HS	120	#undef CONFIG_CMD_SETGETDCR
55ac7a74	121	#undef CONFIG_CMD_XIMG
6b443944 HS	122
	123	#define CONFIG_ATMEL_USART 1
	124	#define CONFIG_MACB 1
	125	#define CONFIG_PIO2 1
	126	#define CFG_NR_PIOS 5
	127	#define CFG_HSDRAMC 1
	128	#define CONFIG_MMC 1
	129
	130	#define CFG_DCACHE_LINESZ 32
	131	#define CFG_ICACHE_LINESZ 32
	132
	133	#define CONFIG_NR_DRAM_BANKS 1
	134
	135	#define CFG_FLASH_CFI 1
	136	#define CFG_FLASH_CFI_DRIVER 1
	137
	138	#define CFG_FLASH_BASE 0x00000000
	139	#define CFG_FLASH_SIZE 0x800000
	140	#define CFG_MAX_FLASH_BANKS 1
	141	#define CFG_MAX_FLASH_SECT 135
	142
	143	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	144
a23e277c HS	145	#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE
	146	#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE
	147	#define CFG_SDRAM_BASE EBI_SDRAM_BASE
6b443944 HS	148
	149	#define CFG_ENV_IS_IN_FLASH 1
	150	#define CFG_ENV_SIZE 65536
	151	#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
	152
	153	#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
	154
	155	#define CFG_MALLOC_LEN (256*1024)
6b443944 HS	156	#define CFG_DMA_ALLOC_LEN (16384)
	157
	158	/* Allow 4MB for the kernel run-time image */
a23e277c	159	#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
6b443944 HS	160	#define CFG_BOOTPARAMS_LEN (16 * 1024)
	161
	162	/* Other configuration settings that shouldn't have to change all that often */
55ac7a74	163	#define CFG_PROMPT "U-Boot> "
6b443944 HS	164	#define CFG_CBSIZE 256
	165	#define CFG_MAXARGS 16
	166	#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
	167	#define CFG_LONGHELP 1
	168
a23e277c	169	#define CFG_MEMTEST_START EBI_SDRAM_BASE
2bcacc2d HS	170	#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
2bcacc2d HS	171
6b443944 HS	172	#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
	173
	174	#endif /* __CONFIG_H */