[people/ms/u-boot.git] / include / configs / atngw100mkii.h

/*
 * Copyright (C) 2006 Atmel Corporation
 *
 * Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
 *
 * Configuration settings for the AVR32 Network Gateway
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_H
#define __CONFIG_H

#include <asm/arch/hardware.h>

#define CONFIG_AT32AP
#define CONFIG_AT32AP7000
#define CONFIG_ATNGW100MKII

#define CONFIG_BOARD_EARLY_INIT_R

/*
 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
 * and the PBA bus to run at 1/4 the PLL frequency.
 */
#define CONFIG_PLL
#define CONFIG_SYS_POWER_MANAGER
#define CONFIG_SYS_OSC0_HZ		20000000
#define CONFIG_SYS_PLL0_DIV		1
#define CONFIG_SYS_PLL0_MUL		7
#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES	16
/*
 * Set the CPU running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
 */
#define CONFIG_SYS_CLKDIV_CPU		0
/*
 * Set the HSB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
 */
#define CONFIG_SYS_CLKDIV_HSB		1
/*
 * Set the PBA running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
 */
#define CONFIG_SYS_CLKDIV_PBA		2
/*
 * Set the PBB running at:
 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
 */
#define CONFIG_SYS_CLKDIV_PBB		1

/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
#define CONFIG_SYS_NR_VM_REGIONS	3

/*
 * The PLLOPT register controls the PLL like this:
 *   icp = PLLOPT<2>
 *   ivco = PLLOPT<1:0>
 *
 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
 */
#define CONFIG_SYS_PLL0_OPT		0x04

#define CONFIG_USART_BASE		ATMEL_BASE_USART1
#define CONFIG_USART_ID			1

/* User serviceable stuff */

#define CONFIG_CMDLINE_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG

#define CONFIG_BOOTARGS							\
	"root=mtd:main rootfstype=jffs2"
#define CONFIG_BOOTCOMMAND						\
	"fsload 0x10400000 /uImage; bootm"


/*
 * After booting the board for the first time, new ethernet addresses
 * should be generated and assigned to the environment variables
 * "ethaddr" and "eth1addr". This is normally done during production.
 */
#define CONFIG_OVERWRITE_ETHADDR_ONCE

/*
 * BOOTP/DHCP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY

/*
 * Command line configuration.
 */

#define CONFIG_ATMEL_USART
#define CONFIG_MACB
#define CONFIG_PORTMUX_PIO
#define CONFIG_SYS_NR_PIOS		5
#define CONFIG_SYS_HSDRAMC
#define CONFIG_GENERIC_ATMEL_MCI
#define CONFIG_ATMEL_SPI

#define CONFIG_SYS_DCACHE_LINESZ	32
#define CONFIG_SYS_ICACHE_LINESZ	32

#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_PROTECTION

#define CONFIG_SYS_FLASH_BASE		0x00000000
#define CONFIG_SYS_FLASH_SIZE		0x800000
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_TEXT_BASE		0x00000000

#define CONFIG_SYS_INTRAM_BASE		INTERNAL_SRAM_BASE
#define CONFIG_SYS_INTRAM_SIZE		INTERNAL_SRAM_SIZE
#define CONFIG_SYS_SDRAM_BASE		EBI_SDRAM_BASE

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SIZE			65536
#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)

#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)

#define CONFIG_SYS_MALLOC_LEN		(256*1024)

/* Allow 4MB for the kernel run-time image */
#define CONFIG_SYS_LOAD_ADDR		(EBI_SDRAM_BASE + 0x00400000)
#define CONFIG_SYS_BOOTPARAMS_LEN	(16 * 1024)

/* Other configuration settings that shouldn't have to change all that often */
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x1f00000)

#define CONFIG_MTD_DEVICE
#define CONFIG_MTD_PARTITIONS

#endif /* __CONFIG_H */
Commit	Line	Data
a420dfe2 AB	1	/*
	2	* Copyright (C) 2006 Atmel Corporation
	3	*
09c2b8f3	4	* Copyright (C) 2012 Andreas Bießmann <andreas@biessmann.org>
a420dfe2 AB	5	*
	6	* Configuration settings for the AVR32 Network Gateway
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
a420dfe2 AB	9	*/
	10	#ifndef __CONFIG_H
	11	#define __CONFIG_H
	12
	13	#include <asm/arch/hardware.h>
	14
a420dfe2 AB	15	#define CONFIG_AT32AP
	16	#define CONFIG_AT32AP7000
	17	#define CONFIG_ATNGW100MKII
	18
ed78b11c AB	19	#define CONFIG_BOARD_EARLY_INIT_R
ed78b11c AB	20
a420dfe2 AB	21	/*
	22	* Set up the PLL to run at 140 MHz, the CPU to run at the PLL
	23	* frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
	24	* and the PBA bus to run at 1/4 the PLL frequency.
	25	*/
	26	#define CONFIG_PLL
	27	#define CONFIG_SYS_POWER_MANAGER
	28	#define CONFIG_SYS_OSC0_HZ 20000000
	29	#define CONFIG_SYS_PLL0_DIV 1
	30	#define CONFIG_SYS_PLL0_MUL 7
	31	#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
	32	/*
	33	* Set the CPU running at:
	34	* PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
	35	*/
	36	#define CONFIG_SYS_CLKDIV_CPU 0
	37	/*
	38	* Set the HSB running at:
	39	* PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
	40	*/
	41	#define CONFIG_SYS_CLKDIV_HSB 1
	42	/*
	43	* Set the PBA running at:
	44	* PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
	45	*/
	46	#define CONFIG_SYS_CLKDIV_PBA 2
	47	/*
	48	* Set the PBB running at:
	49	* PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
	50	*/
	51	#define CONFIG_SYS_CLKDIV_PBB 1
	52
	53	/* Reserve VM regions for NOR flash, NAND flash and SDRAM */
	54	#define CONFIG_SYS_NR_VM_REGIONS 3
	55
	56	/*
	57	* The PLLOPT register controls the PLL like this:
	58	* icp = PLLOPT<2>
	59	* ivco = PLLOPT<1:0>
	60	*
	61	* We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
	62	*/
	63	#define CONFIG_SYS_PLL0_OPT 0x04
	64
	65	#define CONFIG_USART_BASE ATMEL_BASE_USART1
	66	#define CONFIG_USART_ID 1
	67
	68	/* User serviceable stuff */
a420dfe2 AB	69
	70	#define CONFIG_CMDLINE_TAG
	71	#define CONFIG_SETUP_MEMORY_TAGS
	72	#define CONFIG_INITRD_TAG
	73
a420dfe2 AB	74	#define CONFIG_BOOTARGS \
	75	"root=mtd:main rootfstype=jffs2"
	76	#define CONFIG_BOOTCOMMAND \
	77	"fsload 0x10400000 /uImage; bootm"
	78
a420dfe2 AB	79
	80	/*
	81	* After booting the board for the first time, new ethernet addresses
	82	* should be generated and assigned to the environment variables
	83	* "ethaddr" and "eth1addr". This is normally done during production.
	84	*/
	85	#define CONFIG_OVERWRITE_ETHADDR_ONCE
a420dfe2 AB	86
	87	/*
	88	* BOOTP/DHCP options
	89	*/
	90	#define CONFIG_BOOTP_SUBNETMASK
	91	#define CONFIG_BOOTP_GATEWAY
	92
	93	/*
	94	* Command line configuration.
	95	*/
a420dfe2	96
a420dfe2 AB	97	#define CONFIG_ATMEL_USART
	98	#define CONFIG_MACB
	99	#define CONFIG_PORTMUX_PIO
	100	#define CONFIG_SYS_NR_PIOS 5
	101	#define CONFIG_SYS_HSDRAMC
a420dfe2	102	#define CONFIG_GENERIC_ATMEL_MCI
a420dfe2 AB	103	#define CONFIG_ATMEL_SPI
a420dfe2 AB	104
a420dfe2 AB	105	#define CONFIG_SYS_DCACHE_LINESZ 32
	106	#define CONFIG_SYS_ICACHE_LINESZ 32
	107
	108	#define CONFIG_NR_DRAM_BANKS 1
	109
	110	#define CONFIG_SYS_FLASH_CFI
	111	#define CONFIG_FLASH_CFI_DRIVER
	112	#define CONFIG_SYS_FLASH_PROTECTION
	113
	114	#define CONFIG_SYS_FLASH_BASE 0x00000000
	115	#define CONFIG_SYS_FLASH_SIZE 0x800000
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	117	#define CONFIG_SYS_MAX_FLASH_SECT 135
	118
	119	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
024cd741	120	#define CONFIG_SYS_TEXT_BASE 0x00000000
a420dfe2 AB	121
	122	#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
	123	#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
	124	#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
	125
	126	#define CONFIG_ENV_IS_IN_FLASH
	127	#define CONFIG_ENV_SIZE 65536
	128	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
	129
	130	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
	131
	132	#define CONFIG_SYS_MALLOC_LEN (256*1024)
a420dfe2 AB	133
	134	/* Allow 4MB for the kernel run-time image */
	135	#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
	136	#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
	137
	138	/* Other configuration settings that shouldn't have to change all that often */
a420dfe2 AB	139	#define CONFIG_SYS_CBSIZE 256
	140	#define CONFIG_SYS_MAXARGS 16
	141	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	142	#define CONFIG_SYS_LONGHELP
	143
	144	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	145	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x1f00000)
	146
	147	#define CONFIG_MTD_DEVICE
	148	#define CONFIG_MTD_PARTITIONS
	149
	150	#endif /* __CONFIG_H */