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1 | /* |
2 | * Copyright (C) 2005-2006 Atmel Corporation | |
3 | * | |
4 | * Configuration settings for the ATSTK1002 CPU daughterboard | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | #define CONFIG_AVR32 1 | |
28 | #define CONFIG_AT32AP 1 | |
29 | #define CONFIG_AT32AP7000 1 | |
30 | #define CONFIG_ATSTK1002 1 | |
31 | #define CONFIG_ATSTK1000 1 | |
32 | ||
33 | #define CONFIG_ATSTK1000_EXT_FLASH 1 | |
34 | ||
35 | /* | |
36 | * Timer clock frequency. We're using the CPU-internal COUNT register | |
37 | * for this, so this is equivalent to the CPU core clock frequency | |
38 | */ | |
39 | #define CFG_HZ 1000 | |
40 | ||
41 | /* | |
42 | * Set up the PLL to run at 199.5 MHz, the CPU to run at 1/2 the PLL | |
43 | * frequency and the peripherals to run at 1/4 the PLL frequency. | |
44 | */ | |
45 | #define CONFIG_PLL 1 | |
46 | #define CFG_POWER_MANAGER 1 | |
47 | #define CFG_OSC0_HZ 20000000 | |
48 | #define CFG_PLL0_DIV 1 | |
49 | #define CFG_PLL0_MUL 7 | |
50 | #define CFG_PLL0_SUPPRESS_CYCLES 16 | |
51 | #define CFG_CLKDIV_CPU 0 | |
52 | #define CFG_CLKDIV_HSB 1 | |
53 | #define CFG_CLKDIV_PBA 2 | |
54 | #define CFG_CLKDIV_PBB 1 | |
55 | ||
56 | /* | |
57 | * The PLLOPT register controls the PLL like this: | |
58 | * icp = PLLOPT<2> | |
59 | * ivco = PLLOPT<1:0> | |
60 | * | |
61 | * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). | |
62 | */ | |
63 | #define CFG_PLL0_OPT 0x04 | |
64 | ||
df548d3c HS |
65 | #undef CONFIG_USART0 |
66 | #define CONFIG_USART1 1 | |
67 | #undef CONFIG_USART2 | |
68 | #undef CONFIG_USART3 | |
6ccec449 WD |
69 | |
70 | /* User serviceable stuff */ | |
71 | #define CONFIG_CMDLINE_TAG 1 | |
72 | #define CONFIG_SETUP_MEMORY_TAGS 1 | |
73 | #define CONFIG_INITRD_TAG 1 | |
74 | ||
75 | #define CONFIG_STACKSIZE (2048) | |
76 | ||
77 | #define CONFIG_BAUDRATE 115200 | |
78 | #define CONFIG_BOOTARGS \ | |
79 | "console=ttyUS0 root=/dev/mtdblock1 fbmem=600k" | |
80 | ||
81 | #define CONFIG_COMMANDS (CFG_CMD_BDI \ | |
82 | | CFG_CMD_LOADS \ | |
83 | | CFG_CMD_LOADB \ | |
84 | /* | CFG_CMD_IMI */ \ | |
85 | /* | CFG_CMD_CACHE */ \ | |
86 | | CFG_CMD_FLASH \ | |
87 | | CFG_CMD_MEMORY \ | |
88 | /* | CFG_CMD_NET */ \ | |
89 | | CFG_CMD_ENV \ | |
90 | /* | CFG_CMD_IRQ */ \ | |
91 | | CFG_CMD_BOOTD \ | |
92 | | CFG_CMD_CONSOLE \ | |
93 | /* | CFG_CMD_EEPROM */ \ | |
94 | | CFG_CMD_ASKENV \ | |
95 | | CFG_CMD_RUN \ | |
96 | | CFG_CMD_ECHO \ | |
97 | /* | CFG_CMD_I2C */ \ | |
98 | | CFG_CMD_REGINFO \ | |
99 | /* | CFG_CMD_DATE */ \ | |
100 | /* | CFG_CMD_DHCP */ \ | |
101 | /* | CFG_CMD_AUTOSCRIPT */ \ | |
102 | /* | CFG_CMD_MII */ \ | |
103 | | CFG_CMD_MISC \ | |
104 | /* | CFG_CMD_SDRAM */ \ | |
105 | /* | CFG_CMD_DIAG */ \ | |
106 | /* | CFG_CMD_HWFLOW */ \ | |
107 | /* | CFG_CMD_SAVES */ \ | |
108 | /* | CFG_CMD_SPI */ \ | |
109 | /* | CFG_CMD_PING */ \ | |
110 | /* | CFG_CMD_MMC */ \ | |
111 | /* | CFG_CMD_FAT */ \ | |
112 | /* | CFG_CMD_IMLS */ \ | |
113 | /* | CFG_CMD_ITEST */ \ | |
114 | /* | CFG_CMD_EXT2 */ \ | |
115 | ) | |
116 | ||
117 | #include <cmd_confdefs.h> | |
118 | ||
119 | #define CONFIG_ATMEL_USART 1 | |
120 | #define CONFIG_PIO2 1 | |
121 | #define CFG_NR_PIOS 5 | |
122 | #define CFG_HSDRAMC 1 | |
123 | ||
124 | #define CFG_DCACHE_LINESZ 32 | |
125 | #define CFG_ICACHE_LINESZ 32 | |
126 | ||
127 | #define CONFIG_NR_DRAM_BANKS 1 | |
128 | ||
129 | /* External flash on STK1000 */ | |
130 | #if 0 | |
131 | #define CFG_FLASH_CFI 1 | |
132 | #define CFG_FLASH_CFI_DRIVER 1 | |
133 | #endif | |
134 | ||
135 | #define CFG_FLASH_BASE 0x00000000 | |
136 | #define CFG_FLASH_SIZE 0x800000 | |
137 | #define CFG_MAX_FLASH_BANKS 1 | |
138 | #define CFG_MAX_FLASH_SECT 135 | |
139 | ||
140 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
141 | ||
142 | #define CFG_INTRAM_BASE 0x24000000 | |
143 | #define CFG_INTRAM_SIZE 0x8000 | |
144 | ||
145 | #define CFG_SDRAM_BASE 0x10000000 | |
146 | ||
147 | #define CFG_ENV_IS_IN_FLASH 1 | |
148 | #define CFG_ENV_SIZE 65536 | |
149 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) | |
150 | ||
151 | #define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) | |
152 | ||
153 | #define CFG_MALLOC_LEN (256*1024) | |
154 | #define CFG_MALLOC_END \ | |
155 | ({ \ | |
156 | DECLARE_GLOBAL_DATA_PTR; \ | |
157 | CFG_SDRAM_BASE + gd->sdram_size; \ | |
158 | }) | |
159 | #define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN) | |
160 | ||
161 | #define CFG_DMA_ALLOC_LEN (16384) | |
162 | #define CFG_DMA_ALLOC_END (CFG_MALLOC_START) | |
163 | #define CFG_DMA_ALLOC_START (CFG_DMA_ALLOC_END - CFG_DMA_ALLOC_LEN) | |
164 | /* Allow 2MB for the kernel run-time image */ | |
165 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00200000) | |
166 | #define CFG_BOOTPARAMS_LEN (16 * 1024) | |
167 | ||
168 | /* Other configuration settings that shouldn't have to change all that often */ | |
169 | #define CFG_PROMPT "Uboot> " | |
170 | #define CFG_CBSIZE 256 | |
171 | #define CFG_MAXARGS 8 | |
172 | #define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) | |
173 | #define CFG_LONGHELP 1 | |
174 | ||
175 | #define CFG_MEMTEST_START \ | |
176 | ({ DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start; }) | |
177 | #define CFG_MEMTEST_END \ | |
178 | ({ \ | |
179 | DECLARE_GLOBAL_DATA_PTR; \ | |
180 | gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size; \ | |
181 | }) | |
182 | #define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } | |
183 | ||
184 | #endif /* __CONFIG_H */ |