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1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1003 CPU daughterboard
5 *
1a459660 6 * SPDX-License-Identifier: GPL-2.0+
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7 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
5d73bc7a 11#include <asm/arch/hardware.h>
a23e277c 12
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13#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7001
16#define CONFIG_ATSTK1003
17#define CONFIG_ATSTK1000
667568db 18
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19/*
20 * Timer clock frequency. We're using the CPU-internal COUNT register
21 * for this, so this is equivalent to the CPU core clock frequency
22 */
6d0f6bcf 23#define CONFIG_SYS_HZ 1000
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24
25/*
26 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
27 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
28 * PLL frequency.
6d0f6bcf 29 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
667568db 30 */
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31#define CONFIG_PLL
32#define CONFIG_SYS_POWER_MANAGER
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33#define CONFIG_SYS_OSC0_HZ 20000000
34#define CONFIG_SYS_PLL0_DIV 1
35#define CONFIG_SYS_PLL0_MUL 7
36#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
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37/*
38 * Set the CPU running at:
6d0f6bcf 39 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
667568db 40 */
6d0f6bcf 41#define CONFIG_SYS_CLKDIV_CPU 0
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42/*
43 * Set the HSB running at:
6d0f6bcf 44 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
667568db 45 */
6d0f6bcf 46#define CONFIG_SYS_CLKDIV_HSB 1
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47/*
48 * Set the PBA running at:
6d0f6bcf 49 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
667568db 50 */
6d0f6bcf 51#define CONFIG_SYS_CLKDIV_PBA 2
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52/*
53 * Set the PBB running at:
6d0f6bcf 54 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
667568db 55 */
6d0f6bcf 56#define CONFIG_SYS_CLKDIV_PBB 1
667568db 57
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58/* Reserve VM regions for SDRAM and NOR flash */
59#define CONFIG_SYS_NR_VM_REGIONS 2
60
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61/*
62 * The PLLOPT register controls the PLL like this:
63 * icp = PLLOPT<2>
64 * ivco = PLLOPT<1:0>
65 *
66 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
67 */
6d0f6bcf 68#define CONFIG_SYS_PLL0_OPT 0x04
667568db 69
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70#define CONFIG_USART_BASE ATMEL_BASE_USART1
71#define CONFIG_USART_ID 1
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72
73/* User serviceable stuff */
38a39398 74#define CONFIG_DOS_PARTITION
667568db 75
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76#define CONFIG_CMDLINE_TAG
77#define CONFIG_SETUP_MEMORY_TAGS
78#define CONFIG_INITRD_TAG
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79
80#define CONFIG_STACKSIZE (2048)
81
82#define CONFIG_BAUDRATE 115200
83#define CONFIG_BOOTARGS \
84 "console=ttyS0 root=/dev/mmcblk0p1 rootwait"
85
86#define CONFIG_BOOTCOMMAND \
72fa4679 87 "mmc rescan; ext2load mmc 0:1 0x10400000 /boot/uImage; bootm"
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88
89/*
90 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
91 * data on the serial line may interrupt the boot sequence.
92 */
93#define CONFIG_BOOTDELAY 1
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94#define CONFIG_AUTOBOOT
95#define CONFIG_AUTOBOOT_KEYED
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96#define CONFIG_AUTOBOOT_PROMPT \
97 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
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98#define CONFIG_AUTOBOOT_DELAY_STR "d"
99#define CONFIG_AUTOBOOT_STOP_STR " "
100
101/*
102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_ASKENV
107#define CONFIG_CMD_EXT2
108#define CONFIG_CMD_FAT
109#define CONFIG_CMD_JFFS2
110#define CONFIG_CMD_MMC
111
112#undef CONFIG_CMD_FPGA
113#undef CONFIG_CMD_NET
114#undef CONFIG_CMD_NFS
115#undef CONFIG_CMD_SETGETDCR
116#undef CONFIG_CMD_XIMG
117
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118#define CONFIG_ATMEL_USART
119#define CONFIG_PORTMUX_PIO
120#define CONFIG_SYS_HSDRAMC
121#define CONFIG_MMC
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122#define CONFIG_GENERIC_ATMEL_MCI
123#define CONFIG_GENERIC_MMC
667568db 124
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125#define CONFIG_SYS_DCACHE_LINESZ 32
126#define CONFIG_SYS_ICACHE_LINESZ 32
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127
128#define CONFIG_NR_DRAM_BANKS 1
129
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130#define CONFIG_SYS_FLASH_CFI
131#define CONFIG_FLASH_CFI_DRIVER
667568db 132
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133#define CONFIG_SYS_FLASH_BASE 0x00000000
134#define CONFIG_SYS_FLASH_SIZE 0x800000
135#define CONFIG_SYS_MAX_FLASH_BANKS 1
136#define CONFIG_SYS_MAX_FLASH_SECT 135
667568db 137
6d0f6bcf 138#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
47293c18 139#define CONFIG_SYS_TEXT_BASE 0x00000000
667568db 140
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141#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
142#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
143#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
667568db 144
38a39398 145#define CONFIG_ENV_IS_IN_FLASH
0e8d1586 146#define CONFIG_ENV_SIZE 65536
6d0f6bcf 147#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
667568db 148
6d0f6bcf 149#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
667568db 150
6d0f6bcf 151#define CONFIG_SYS_MALLOC_LEN (256*1024)
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152
153/* Allow 4MB for the kernel run-time image */
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154#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
155#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
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156
157/* Other configuration settings that shouldn't have to change all that often */
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158#define CONFIG_SYS_PROMPT "U-Boot> "
159#define CONFIG_SYS_CBSIZE 256
160#define CONFIG_SYS_MAXARGS 16
161#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
38a39398 162#define CONFIG_SYS_LONGHELP
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163
164#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
165#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x700000)
166#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
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167
168#endif /* __CONFIG_H */