[people/ms/u-boot.git] / include / configs / axs101.h

/*
 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _CONFIG_AXS101_H_
#define _CONFIG_AXS101_H_

/*
 *  CPU configuration
 */
#define CONFIG_ARC700
#define CONFIG_ARC_MMU_VER		3
#define CONFIG_SYS_CACHELINE_SIZE	32
#define CONFIG_SYS_CLK_FREQ		750000000
#define CONFIG_SYS_TIMER_RATE		CONFIG_SYS_CLK_FREQ

/* dwgmac doesn't work with D$ enabled now */
#define CONFIG_SYS_DCACHE_OFF

/*
 * Board configuration
 */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_SKIP_LOWLEVEL_INIT	/* U-Boot is in RAM already */

#define CONFIG_ARCH_EARLY_INIT_R

#define ARC_FPGA_PERIPHERAL_BASE	0xE0000000
#define ARC_APB_PERIPHERAL_BASE		0xF0000000
#define ARC_DWMMC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x15000)
#define ARC_DWGMAC_BASE			(ARC_FPGA_PERIPHERAL_BASE + 0x18000)

/*
 * Memory configuration
 */
#define CONFIG_SYS_TEXT_BASE		0x81000000
#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE

#define CONFIG_SYS_DDR_SDRAM_BASE	0x80000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE		0x10000000	/* 256 Mb */

#define CONFIG_SYS_INIT_SP_ADDR		\
	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MALLOC_LEN		0x200000	/* 2 MB */
#define CONFIG_SYS_BOOTM_LEN		0x2000000	/* 32 MB */
#define CONFIG_SYS_LOAD_ADDR		0x82000000

/*
 * NAND Flash configuration
 */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_NAND_BASE		(ARC_FPGA_PERIPHERAL_BASE + 0x16000)
#define CONFIG_SYS_MAX_NAND_DEVICE	1

/*
 * UART configuration
 *
 * CONFIG_CONS_INDEX = 1 - Debug UART
 * CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
 */
#define CONFIG_CONS_INDEX		4
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#if (CONFIG_CONS_INDEX == 1)
	/* Debug UART */
#	define CONFIG_SYS_NS16550_CLK		33333000
#else
	/* FPGA UARTs use different clock */
#	define CONFIG_SYS_NS16550_CLK		33333333
#endif
#define CONFIG_SYS_NS16550_COM1		(ARC_APB_PERIPHERAL_BASE + 0x5000)
#define CONFIG_SYS_NS16550_COM2		(ARC_FPGA_PERIPHERAL_BASE + 0x20000)
#define CONFIG_SYS_NS16550_COM3		(ARC_FPGA_PERIPHERAL_BASE + 0x21000)
#define CONFIG_SYS_NS16550_COM4		(ARC_FPGA_PERIPHERAL_BASE + 0x22000)
#define CONFIG_SYS_NS16550_MEM32

#define CONFIG_BAUDRATE			115200
/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C
#define CONFIG_DW_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_ENV_EEPROM_BUS	2
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SLAVE		0
#define CONFIG_SYS_I2C_BASE		0xE001D000
#define CONFIG_SYS_I2C_BASE1		0xE001E000
#define CONFIG_SYS_I2C_BASE2		0xE001F000
#define CONFIG_SYS_I2C_BUS_MAX		3
#define IC_CLK				50

/*
 * EEPROM configuration
 */
#define CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR		(0xA8 >> 1)
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		1
#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW	1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	32

/*
 * SD/MMC configuration
 */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_DWMMC
#define CONFIG_DOS_PARTITION

/*
 * Ethernet PHY configuration
 */
#define CONFIG_PHYLIB
#define CONFIG_MII
#define CONFIG_PHY_GIGE

/*
 * Ethernet configuration
 */
#define CONFIG_DESIGNWARE_ETH
#define CONFIG_DW_AUTONEG
#define CONFIG_DW_SEARCH_PHY
#define CONFIG_NET_MULTI

/*
 * Command line configuration
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FAT
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MMC
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PING
#define CONFIG_CMD_RARP

#define CONFIG_OF_LIBFDT

#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_MAXARGS		16

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_EEPROM
#define CONFIG_ENV_SIZE			0x00200		/* 512 bytes */
#define CONFIG_ENV_OFFSET		0

/*
 * Environment configuration
 */
#define CONFIG_BOOTDELAY		3
#define CONFIG_BOOTFILE			"uImage"
#define CONFIG_BOOTARGS			"console=ttyS3,115200n8"
#define CONFIG_LOADADDR			CONFIG_SYS_LOAD_ADDR

/*
 * Console configuration
 */
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT		"AXS# "
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
						sizeof(CONFIG_SYS_PROMPT) + 16)

/*
 * Misc utility configuration
 */
#define CONFIG_BOUNCE_BUFFER

#endif /* _CONFIG_AXS101_H_ */
Commit	Line	Data
a7069ddf AB	1	/*
	2	* Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#ifndef _CONFIG_AXS101_H_
	8	#define _CONFIG_AXS101_H_
	9
	10	/*
	11	* CPU configuration
	12	*/
	13	#define CONFIG_ARC700
	14	#define CONFIG_ARC_MMU_VER 3
	15	#define CONFIG_SYS_CACHELINE_SIZE 32
	16	#define CONFIG_SYS_CLK_FREQ 750000000
	17	#define CONFIG_SYS_TIMER_RATE CONFIG_SYS_CLK_FREQ
	18
	19	/* dwgmac doesn't work with D$ enabled now */
	20	#define CONFIG_SYS_DCACHE_OFF
	21
	22	/*
	23	* Board configuration
	24	*/
	25	#define CONFIG_SYS_GENERIC_BOARD
	26	#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is in RAM already */
	27
	28	#define CONFIG_ARCH_EARLY_INIT_R
	29
	30	#define ARC_FPGA_PERIPHERAL_BASE 0xE0000000
	31	#define ARC_APB_PERIPHERAL_BASE 0xF0000000
	32	#define ARC_DWMMC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x15000)
	33	#define ARC_DWGMAC_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x18000)
	34
	35	/*
	36	* Memory configuration
	37	*/
	38	#define CONFIG_SYS_TEXT_BASE 0x81000000
	39	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	40
	41	#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
	42	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	43	#define CONFIG_SYS_SDRAM_SIZE 0x10000000 /* 256 Mb */
	44
	45	#define CONFIG_SYS_INIT_SP_ADDR \
	46	(CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE)
	47
	48	#define CONFIG_SYS_MALLOC_LEN 0x200000 /* 2 MB */
	49	#define CONFIG_SYS_BOOTM_LEN 0x2000000 /* 32 MB */
	50	#define CONFIG_SYS_LOAD_ADDR 0x82000000
	51
	52	/*
	53	* NAND Flash configuration
	54	*/
	55	#define CONFIG_SYS_NO_FLASH
	56	#define CONFIG_SYS_NAND_BASE (ARC_FPGA_PERIPHERAL_BASE + 0x16000)
	57	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	58
	59	/*
	60	* UART configuration
	61	*
	62	* CONFIG_CONS_INDEX = 1 - Debug UART
	63	* CONFIG_CONS_INDEX = 4 - FPGA UART connected to FTDI/USB
	64	*/
65	#define CONFIG_CONS_INDEX 4
66	#define CONFIG_SYS_NS16550
67	#define CONFIG_SYS_NS16550_SERIAL
68	#define CONFIG_SYS_NS16550_REG_SIZE -4
69	#if (CONFIG_CONS_INDEX == 1)
70	/* Debug UART */
71	# define CONFIG_SYS_NS16550_CLK 33333000
72	#else
73	/* FPGA UARTs use different clock */
74	# define CONFIG_SYS_NS16550_CLK 33333333
75	#endif
76	#define CONFIG_SYS_NS16550_COM1 (ARC_APB_PERIPHERAL_BASE + 0x5000)
77	#define CONFIG_SYS_NS16550_COM2 (ARC_FPGA_PERIPHERAL_BASE + 0x20000)
78	#define CONFIG_SYS_NS16550_COM3 (ARC_FPGA_PERIPHERAL_BASE + 0x21000)
79	#define CONFIG_SYS_NS16550_COM4 (ARC_FPGA_PERIPHERAL_BASE + 0x22000)
80	#define CONFIG_SYS_NS16550_MEM32
81
82	#define CONFIG_BAUDRATE 115200
83	/*
84	* I2C configuration
85	*/
86	#define CONFIG_HARD_I2C
87	#define CONFIG_DW_I2C
88	#define CONFIG_I2C_MULTI_BUS
89	#define CONFIG_I2C_ENV_EEPROM_BUS 2
90	#define CONFIG_SYS_I2C_SPEED 100000
91	#define CONFIG_SYS_I2C_SLAVE 0
92	#define CONFIG_SYS_I2C_BASE 0xE001D000
93	#define CONFIG_SYS_I2C_BASE1 0xE001E000
94	#define CONFIG_SYS_I2C_BASE2 0xE001F000
95	#define CONFIG_SYS_I2C_BUS_MAX 3
96	#define IC_CLK 50
97
98	/*
99	* EEPROM configuration
100	*/
101	#define CONFIG_SYS_I2C_MULTI_EEPROMS
102	#define CONFIG_SYS_I2C_EEPROM_ADDR (0xA8 >> 1)
103	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
104	#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 1
105	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
106	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 32
107
108	/*
109	* SD/MMC configuration
110	*/
111	#define CONFIG_MMC
112	#define CONFIG_GENERIC_MMC
113	#define CONFIG_DWMMC
114	#define CONFIG_DOS_PARTITION
115
116	/*
117	* Ethernet PHY configuration
118	*/
119	#define CONFIG_PHYLIB
120	#define CONFIG_MII
121	#define CONFIG_PHY_GIGE
122
123	/*
124	* Ethernet configuration
125	*/
126	#define CONFIG_DESIGNWARE_ETH
127	#define CONFIG_DW_AUTONEG
128	#define CONFIG_DW_SEARCH_PHY
129	#define CONFIG_NET_MULTI
130
131	/*
132	* Command line configuration
133	*/
134	#include <config_cmd_default.h>
135
136	#define CONFIG_CMD_DHCP
137	#define CONFIG_CMD_EEPROM
138	#define CONFIG_CMD_ELF
139	#define CONFIG_CMD_FAT
140	#define CONFIG_CMD_I2C
141	#define CONFIG_CMD_MMC
142	#define CONFIG_CMD_NAND
143	#define CONFIG_CMD_PING
144	#define CONFIG_CMD_RARP
145
146	#define CONFIG_OF_LIBFDT
147
148	#define CONFIG_AUTO_COMPLETE
149	#define CONFIG_SYS_MAXARGS 16
150
151	/*
152	* Environment settings
153	*/
154	#define CONFIG_ENV_IS_IN_EEPROM
155	#define CONFIG_ENV_SIZE 0x00200 /* 512 bytes */
156	#define CONFIG_ENV_OFFSET 0
157
158	/*
159	* Environment configuration
160	*/
161	#define CONFIG_BOOTDELAY 3
162	#define CONFIG_BOOTFILE "uImage"
163	#define CONFIG_BOOTARGS "console=ttyS3,115200n8"
164	#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
165
166	/*
167	* Console configuration
168	*/
169	#define CONFIG_SYS_LONGHELP
c42eb7f2	170	#define CONFIG_SYS_PROMPT "AXS# "
a7069ddf AB	171	#define CONFIG_SYS_CBSIZE 256
	172	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	173	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	174	sizeof(CONFIG_SYS_PROMPT) + 16)
	175
	176	/*
	177	* Misc utility configuration
	178	*/
	179	#define CONFIG_BOUNCE_BUFFER
	180
	181	#endif /* _CONFIG_AXS101_H_ */