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8a316c9b | 1 | /* |
8b39501d | 2 | * (C) Copyright 2005-2007 |
8a316c9b SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /************************************************************************ | |
25 | * bamboo.h - configuration for BAMBOO board | |
26 | ***********************************************************************/ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /*----------------------------------------------------------------------- | |
31 | * High Level Configuration Options | |
32 | *----------------------------------------------------------------------*/ | |
17f50f22 | 33 | #define CONFIG_BAMBOO 1 /* Board is BAMBOO */ |
846b0dd2 | 34 | #define CONFIG_440EP 1 /* Specific PPC440EP support */ |
efa35cf1 | 35 | #define CONFIG_440 1 /* ... PPC440 family */ |
17f50f22 | 36 | #define CONFIG_4xx 1 /* ... PPC4xx family */ |
8a316c9b SR |
37 | #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ |
38 | ||
490f2040 SR |
39 | /* |
40 | * Include common defines/options for all AMCC eval boards | |
41 | */ | |
42 | #define CONFIG_HOSTNAME bamboo | |
43 | #include "amcc-common.h" | |
44 | ||
c57c7980 SR |
45 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
46 | ||
47 | /* | |
48 | * Please note that, if NAND support is enabled, the 2nd ethernet port | |
49 | * can't be used because of pin multiplexing. So, if you want to use the | |
50 | * 2nd ethernet port you have to "undef" the following define. | |
51 | */ | |
52 | #define CONFIG_BAMBOO_NAND 1 /* enable nand flash support */ | |
53 | ||
8a316c9b SR |
54 | /*----------------------------------------------------------------------- |
55 | * Base addresses -- Note these are effective addresses where the | |
56 | * actual resources get mapped (not physical addresses) | |
57 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
58 | #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ |
59 | #define CONFIG_SYS_PCI_MEMBASE 0xa0000000 /* mapped pci memory*/ | |
60 | #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 | |
61 | #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 | |
62 | #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 | |
8a316c9b SR |
63 | |
64 | /*Don't change either of these*/ | |
550650dd | 65 | #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ |
8a316c9b SR |
66 | /*Don't change either of these*/ |
67 | ||
6d0f6bcf JCPV |
68 | #define CONFIG_SYS_USB_DEVICE 0x50000000 |
69 | #define CONFIG_SYS_NVRAM_BASE_ADDR 0x80000000 | |
70 | #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000 | |
71 | #define CONFIG_SYS_NAND_ADDR 0x90000000 | |
72 | #define CONFIG_SYS_NAND2_ADDR 0x94000000 | |
8a316c9b SR |
73 | |
74 | /*----------------------------------------------------------------------- | |
75 | * Initial RAM & stack pointer (placed in SDRAM) | |
76 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */ |
78 | #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */ | |
79 | #define CONFIG_SYS_INIT_RAM_END (4 << 10) | |
80 | #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */ | |
81 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
82 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
8a316c9b | 83 | |
8a316c9b SR |
84 | /*----------------------------------------------------------------------- |
85 | * Serial Port | |
86 | *----------------------------------------------------------------------*/ | |
550650dd | 87 | #define CONFIG_CONS_INDEX 1 /* Use UART0 */ |
6d0f6bcf | 88 | #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ |
8a316c9b | 89 | |
8a316c9b SR |
90 | /*----------------------------------------------------------------------- |
91 | * NVRAM/RTC | |
92 | * | |
93 | * NOTE: The RTC registers are located at 0x7FFF0 - 0x7FFFF | |
94 | * The DS1558 code assumes this condition | |
95 | * | |
96 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 97 | #define CONFIG_SYS_NVRAM_SIZE (0x2000 - 0x10) /* NVRAM size(8k)- RTC regs */ |
17f50f22 SR |
98 | #define CONFIG_RTC_DS1556 1 /* DS1556 RTC */ |
99 | ||
100 | /*----------------------------------------------------------------------- | |
101 | * Environment | |
102 | *----------------------------------------------------------------------*/ | |
cf959c7d | 103 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
5a1aceb0 | 104 | #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ |
17f50f22 | 105 | #else |
51bfee19 | 106 | #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ |
0e8d1586 | 107 | #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */ |
17f50f22 | 108 | #endif |
8a316c9b SR |
109 | |
110 | /*----------------------------------------------------------------------- | |
111 | * FLASH related | |
112 | *----------------------------------------------------------------------*/ | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* number of banks */ |
114 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ | |
8a316c9b | 115 | |
6d0f6bcf JCPV |
116 | #undef CONFIG_SYS_FLASH_CHECKSUM |
117 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
118 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
8a316c9b | 119 | |
6d0f6bcf JCPV |
120 | #define CONFIG_SYS_FLASH_ADDR0 0x555 |
121 | #define CONFIG_SYS_FLASH_ADDR1 0x2aa | |
122 | #define CONFIG_SYS_FLASH_WORD_SIZE unsigned char | |
8a316c9b | 123 | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */ |
125 | #define CONFIG_SYS_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */ | |
8a316c9b | 126 | |
5a1aceb0 | 127 | #ifdef CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 128 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ |
6d0f6bcf | 129 | #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE) |
0e8d1586 | 130 | #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ |
17f50f22 | 131 | |
17f50f22 | 132 | /* Address and size of Redundant Environment Sector */ |
0e8d1586 JCPV |
133 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE) |
134 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
5a1aceb0 | 135 | #endif /* CONFIG_ENV_IS_IN_FLASH */ |
8a316c9b | 136 | |
cf959c7d SR |
137 | /* |
138 | * IPL (Initial Program Loader, integrated inside CPU) | |
139 | * Will load first 4k from NAND (SPL) into cache and execute it from there. | |
140 | * | |
141 | * SPL (Secondary Program Loader) | |
142 | * Will load special U-Boot version (NUB) from NAND and execute it. This SPL | |
143 | * has to fit into 4kByte. It sets up the CPU and configures the SDRAM | |
144 | * controller and the NAND controller so that the special U-Boot image can be | |
145 | * loaded from NAND to SDRAM. | |
146 | * | |
147 | * NUB (NAND U-Boot) | |
148 | * This NAND U-Boot (NUB) is a special U-Boot version which can be started | |
149 | * from RAM. Therefore it mustn't (re-)configure the SDRAM controller. | |
150 | * | |
151 | * On 440EPx the SPL is copied to SDRAM before the NAND controller is | |
152 | * set up. While still running from cache, I experienced problems accessing | |
153 | * the NAND controller. sr - 2006-08-25 | |
154 | */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */ |
156 | #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */ | |
157 | #define CONFIG_SYS_NAND_BOOT_SPL_DST 0x00800000 /* Copy SPL here */ | |
158 | #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */ | |
159 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr */ | |
160 | #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST) | |
cf959c7d SR |
161 | |
162 | /* | |
163 | * Define the partitioning of the NAND chip (only RAM U-Boot is needed here) | |
164 | */ | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (16 << 10) /* Offset to RAM U-Boot image */ |
166 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (384 << 10) /* Size of RAM U-Boot image */ | |
cf959c7d SR |
167 | |
168 | /* | |
169 | * Now the NAND chip has to be defined (no autodetection used!) | |
170 | */ | |
6d0f6bcf JCPV |
171 | #define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */ |
172 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10) /* NAND chip block size */ | |
173 | #define CONFIG_SYS_NAND_PAGE_COUNT 32 /* NAND chip page count */ | |
174 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 5 /* Location of bad block marker */ | |
175 | #define CONFIG_SYS_NAND_4_ADDR_CYCLE 1 /* Fourth addr used (>32MB) */ | |
176 | ||
177 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
178 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
179 | #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE) | |
180 | #define CONFIG_SYS_NAND_OOBSIZE 16 | |
181 | #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS) | |
182 | #define CONFIG_SYS_NAND_ECCPOS {0, 1, 2, 3, 6, 7} | |
cf959c7d | 183 | |
51bfee19 | 184 | #ifdef CONFIG_ENV_IS_IN_NAND |
cf959c7d SR |
185 | /* |
186 | * For NAND booting the environment is embedded in the U-Boot image. Please take | |
187 | * look at the file board/amcc/sequoia/u-boot-nand.lds for details. | |
188 | */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
190 | #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE) | |
0e8d1586 | 191 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE) |
cf959c7d SR |
192 | #endif |
193 | ||
c57c7980 | 194 | /*----------------------------------------------------------------------- |
8b39501d | 195 | * NAND FLASH |
c57c7980 | 196 | *----------------------------------------------------------------------*/ |
6d0f6bcf | 197 | #define CONFIG_SYS_MAX_NAND_DEVICE 2 |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS) |
199 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_ADDR + 2 } | |
200 | #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ | |
c57c7980 | 201 | |
cf959c7d | 202 | #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) |
6d0f6bcf | 203 | #define CONFIG_SYS_NAND_CS 1 |
cf959c7d | 204 | #else |
6d0f6bcf | 205 | #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */ |
cf959c7d | 206 | /* Memory Bank 0 (NAND-FLASH) initialization */ |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_EBC_PB0AP 0x018003c0 |
208 | #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1c000) | |
cf959c7d SR |
209 | #endif |
210 | ||
8a316c9b SR |
211 | /*----------------------------------------------------------------------- |
212 | * DDR SDRAM | |
17f50f22 SR |
213 | *----------------------------------------------------------------------------- */ |
214 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ | |
fd49bf02 | 215 | #undef CONFIG_DDR_ECC /* don't use ECC */ |
6d0f6bcf JCPV |
216 | #define CONFIG_SYS_SIMULATE_SPD_EEPROM 0xff /* simulate spd eeprom on this address */ |
217 | #define SPD_EEPROM_ADDRESS {CONFIG_SYS_SIMULATE_SPD_EEPROM, 0x50, 0x51} | |
218 | #define CONFIG_SYS_MBYTES_SDRAM (64) /* 64MB fixed size for early-sdram-init */ | |
d2f68006 | 219 | #define CONFIG_PROG_SDRAM_TLB |
8a316c9b SR |
220 | |
221 | /*----------------------------------------------------------------------- | |
222 | * I2C | |
223 | *----------------------------------------------------------------------*/ | |
6d0f6bcf | 224 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
8a316c9b | 225 | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_I2C_MULTI_EEPROMS |
227 | #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1) | |
228 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
229 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
230 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
8a316c9b | 231 | |
bb1f8b4f | 232 | #ifdef CONFIG_ENV_IS_IN_EEPROM |
0e8d1586 JCPV |
233 | #define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ |
234 | #define CONFIG_ENV_OFFSET 0x0 | |
bb1f8b4f | 235 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
17f50f22 | 236 | |
490f2040 SR |
237 | /* |
238 | * Default environment variables | |
239 | */ | |
17f50f22 | 240 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
490f2040 SR |
241 | CONFIG_AMCC_DEF_ENV \ |
242 | CONFIG_AMCC_DEF_ENV_POWERPC \ | |
243 | CONFIG_AMCC_DEF_ENV_PPC_OLD \ | |
244 | CONFIG_AMCC_DEF_ENV_NOR_UPD \ | |
245 | CONFIG_AMCC_DEF_ENV_NAND_UPD \ | |
17f50f22 SR |
246 | "kernel_addr=fff00000\0" \ |
247 | "ramdisk_addr=fff10000\0" \ | |
17f50f22 | 248 | "" |
8a316c9b | 249 | |
a00eccfe | 250 | #define CONFIG_HAS_ETH0 |
17f50f22 | 251 | #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ |
d6c61aab | 252 | #define CONFIG_PHY1_ADDR 1 |
c57c7980 SR |
253 | |
254 | #ifndef CONFIG_BAMBOO_NAND | |
8a316c9b | 255 | #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ |
c57c7980 SR |
256 | #endif /* CONFIG_BAMBOO_NAND */ |
257 | ||
846b0dd2 | 258 | #ifdef CONFIG_440EP |
8a316c9b SR |
259 | /* USB */ |
260 | #define CONFIG_USB_OHCI | |
261 | #define CONFIG_USB_STORAGE | |
262 | ||
263 | /*Comment this out to enable USB 1.1 device*/ | |
264 | #define USB_2_0_DEVICE | |
846b0dd2 | 265 | #endif /*CONFIG_440EP*/ |
8a316c9b | 266 | |
80ff4f99 | 267 | /* |
490f2040 | 268 | * Commands additional to the ones defined in amcc-common.h |
80ff4f99 | 269 | */ |
ba2351f9 | 270 | #define CONFIG_CMD_DATE |
490f2040 SR |
271 | #define CONFIG_CMD_EXT2 |
272 | #define CONFIG_CMD_FAT | |
ba2351f9 | 273 | #define CONFIG_CMD_PCI |
ba2351f9 | 274 | #define CONFIG_CMD_SDRAM |
ba2351f9 | 275 | #define CONFIG_CMD_SNTP |
490f2040 | 276 | #define CONFIG_CMD_USB |
ba2351f9 | 277 | |
c57c7980 | 278 | #ifdef CONFIG_BAMBOO_NAND |
ba2351f9 JL |
279 | #define CONFIG_CMD_NAND |
280 | #endif | |
c57c7980 | 281 | |
3b6748ea SR |
282 | #define CONFIG_SUPPORT_VFAT |
283 | ||
490f2040 SR |
284 | /* Partitions */ |
285 | #define CONFIG_MAC_PARTITION | |
286 | #define CONFIG_DOS_PARTITION | |
287 | #define CONFIG_ISO_PARTITION | |
193dd958 | 288 | |
8a316c9b SR |
289 | /*----------------------------------------------------------------------- |
290 | * PCI stuff | |
291 | *----------------------------------------------------------------------- | |
292 | */ | |
293 | /* General PCI */ | |
c57c7980 SR |
294 | #define CONFIG_PCI /* include pci support */ |
295 | #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */ | |
17f50f22 | 296 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
6d0f6bcf | 297 | #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/ |
8a316c9b SR |
298 | |
299 | /* Board-specific PCI */ | |
6d0f6bcf JCPV |
300 | #define CONFIG_SYS_PCI_TARGET_INIT |
301 | #define CONFIG_SYS_PCI_MASTER_INIT | |
8a316c9b | 302 | |
6d0f6bcf JCPV |
303 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */ |
304 | #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */ | |
8a316c9b | 305 | |
8a316c9b | 306 | #endif /* __CONFIG_H */ |