[people/ms/u-boot.git] / include / configs / bf518f-ezbrd.h

/*
 * U-boot - Configuration file for BF518F EZBrd board
 */

#ifndef __CONFIG_BF518F_EZBRD_H__
#define __CONFIG_BF518F_EZBRD_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf518-0.0
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			16
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5


/*
 * Memory Settings
 */
/* This board has a 64meg MT48H32M16 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x0096
#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | CL_3 | PASR_ALL | TRAS_6 | TRP_3 | TRCD_3 | TWR_2 | PSS)

#define CONFIG_EBIU_AMGCTL_VAL	(AMCKEN | AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_15 | B1RAT_15 | B1HT_3 | B1RDYPOL | B0WAT_15 | B0RAT_15 | B0HT_3 | B0RDYPOL)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_15 | B3RAT_15 | B3HT_3 | B3RDYPOL | B2WAT_15 | B2RAT_15 | B2HT_3 | B2RDYPOL)

#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)


/*
 * Network Settings
 */
#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_BFIN_MAC_PINS \
	{ \
	P_MII0_ETxD0, \
	P_MII0_ETxD1, \
	P_MII0_ETxD2, \
	P_MII0_ETxD3, \
	P_MII0_ETxEN, \
	P_MII0_TxCLK, \
	P_MII0_PHYINT, \
	P_MII0_COL, \
	P_MII0_ERxD0, \
	P_MII0_ERxD1, \
	P_MII0_ERxD2, \
	P_MII0_ERxD3, \
	P_MII0_ERxDV, \
	P_MII0_ERxCLK, \
	P_MII0_CRS, \
	P_MII0_MDC, \
	P_MII0_MDIO, \
	0 }
#define CONFIG_NETCONSOLE	1
#endif
#define CONFIG_HOSTNAME		bf518f-ezbrd
#define CONFIG_PHY_ADDR		3
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
#define CONFIG_LIB_RAND

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_SST
#define CONFIG_SPI_FLASH_STMICRO


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR


/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI


/*
 * SDH Settings
 */
#if !defined(__ADSPBF512__)
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif


/*
 * Misc Settings
 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
84a9dda3 MF	1	/*
	2	* U-boot - Configuration file for BF518F EZBrd board
	3	*/
	4
	5	#ifndef __CONFIG_BF518F_EZBRD_H__
	6	#define __CONFIG_BF518F_EZBRD_H__
	7
f348ab85	8	#include <asm/config-pre.h>
84a9dda3 MF	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf518-0.0
84a9dda3 MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 16
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 5
	40
	41
	42	/*
	43	* Memory Settings
	44	*/
	45	/* This board has a 64meg MT48H32M16 */
	46	#define CONFIG_MEM_ADD_WDTH 10
	47	#define CONFIG_MEM_SIZE 64
	48
	49	#define CONFIG_EBIU_SDRRC_VAL 0x0096
	50	#define CONFIG_EBIU_SDGCTL_VAL (SCTLE \| CL_3 \| PASR_ALL \| TRAS_6 \| TRP_3 \| TRCD_3 \| TWR_2 \| PSS)
	51
	52	#define CONFIG_EBIU_AMGCTL_VAL (AMCKEN \| AMBEN_ALL)
	53	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_15 \| B1RAT_15 \| B1HT_3 \| B1RDYPOL \| B0WAT_15 \| B0RAT_15 \| B0HT_3 \| B0RDYPOL)
	54	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_15 \| B3RAT_15 \| B3HT_3 \| B3RDYPOL \| B2WAT_15 \| B2RAT_15 \| B2HT_3 \| B2RDYPOL)
	55
912da8d6	56	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
84a9dda3 MF	57	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
	58
	59
	60	/*
	61	* Network Settings
	62	*/
	63	#if !defined(__ADSPBF512__) && !defined(__ADSPBF514__)
	64	#define ADI_CMDS_NETWORK 1
	65	#define CONFIG_BFIN_MAC
0c929426 MF	66	#define CONFIG_BFIN_MAC_PINS \
	67	{ \
	68	P_MII0_ETxD0, \
	69	P_MII0_ETxD1, \
	70	P_MII0_ETxD2, \
	71	P_MII0_ETxD3, \
	72	P_MII0_ETxEN, \
	73	P_MII0_TxCLK, \
	74	P_MII0_PHYINT, \
	75	P_MII0_COL, \
	76	P_MII0_ERxD0, \
	77	P_MII0_ERxD1, \
	78	P_MII0_ERxD2, \
	79	P_MII0_ERxD3, \
	80	P_MII0_ERxDV, \
	81	P_MII0_ERxCLK, \
	82	P_MII0_CRS, \
	83	P_MII0_MDC, \
	84	P_MII0_MDIO, \
	85	0 }
84a9dda3	86	#define CONFIG_NETCONSOLE 1
84a9dda3 MF	87	#endif
	88	#define CONFIG_HOSTNAME bf518f-ezbrd
	89	#define CONFIG_PHY_ADDR 3
	90	/* Uncomment next line to use fixed MAC address */
	91	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
c42f56d9	92	#define CONFIG_LIB_RAND
84a9dda3 MF	93
	94	/*
	95	* Flash Settings
	96	*/
	97	#define CONFIG_FLASH_CFI_DRIVER
	98	#define CONFIG_SYS_FLASH_BASE 0x20000000
	99	#define CONFIG_SYS_FLASH_CFI
	100	#define CONFIG_SYS_FLASH_PROTECTION
	101	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	102	#define CONFIG_SYS_MAX_FLASH_SECT 71
	103
	104
	105	/*
	106	* SPI Settings
	107	*/
	108	#define CONFIG_BFIN_SPI
	109	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	110	#define CONFIG_SF_DEFAULT_SPEED 30000000
84a9dda3	111	#define CONFIG_SPI_FLASH
f52efcae	112	#define CONFIG_SPI_FLASH_SST
84a9dda3 MF	113	#define CONFIG_SPI_FLASH_STMICRO
	114
	115
	116	/*
	117	* Env Storage Settings
	118	*/
	119	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	120	#define CONFIG_ENV_IS_IN_SPI_FLASH
	121	#define CONFIG_ENV_OFFSET 0x10000
	122	#define CONFIG_ENV_SIZE 0x2000
	123	#define CONFIG_ENV_SECT_SIZE 0x10000
	124	#else
	125	#define CONFIG_ENV_IS_IN_FLASH
	126	#define CONFIG_ENV_OFFSET 0x4000
	127	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	128	#define CONFIG_ENV_SIZE 0x2000
	129	#define CONFIG_ENV_SECT_SIZE 0x2000
	130	#endif
76d82187	131	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
84a9dda3 MF	132
	133
	134	/*
	135	* I2C Settings
	136	*/
c469703b	137	#define CONFIG_SYS_I2C
fea9b69a	138	#define CONFIG_SYS_I2C_ADI
84a9dda3 MF	139
	140
	141	/*
	142	* SDH Settings
	143	*/
	144	#if !defined(__ADSPBF512__)
e54c8209	145	#define CONFIG_GENERIC_MMC
84a9dda3 MF	146	#define CONFIG_MMC
	147	#define CONFIG_BFIN_SDH
	148	#endif
	149
	150
	151	/*
	152	* Misc Settings
	153	*/
ab687907	154	#define CONFIG_BOARD_EARLY_INIT_F
84a9dda3 MF	155	#define CONFIG_MISC_INIT_R
	156	#define CONFIG_RTC_BFIN
	157	#define CONFIG_UART_CONSOLE 0
84a9dda3 MF	158
	159	/*
	160	* Pull in common ADI header for remaining command/environment setup
	161	*/
	162	#include <configs/bfin_adi_common.h>
	163
84a9dda3	164	#endif