[people/ms/u-boot.git] / include / configs / bf533-ezkit.h

/*
 * U-Boot - Configuration file for BF533 EZKIT board
 */

#ifndef __CONFIG_BF533_EZKIT_H__
#define __CONFIG_BF533_EZKIT_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf533-0.3
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			27000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			22
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5

/*
 * Memory Settings
 */
#define CONFIG_MEM_SIZE		32
/* Early EZKITs had 32megs, but later have 64megs */
#if (CONFIG_MEM_SIZE == 64)
# define CONFIG_MEM_ADD_WDTH	10
#else
# define CONFIG_MEM_ADD_WDTH	9
#endif

#define CONFIG_EBIU_SDRRC_VAL	0x398
#define CONFIG_EBIU_SDGCTL_VAL	0x91118d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)

/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20310300
#define SMC91111_EEPROM_INIT() \
	do { \
		bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
		bfin_write_FIO_FLAG_C(PF1); \
		bfin_write_FIO_FLAG_S(PF0); \
		SSYNC(); \
	} while (0)
#define CONFIG_HOSTNAME		bf533-ezkit

/*
 * Flash Settings
 */
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_MAX_FLASH_BANKS	3
#define CONFIG_SYS_MAX_FLASH_SECT	40
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR		0x20030000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define FLASH_TOT_SECT		40

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C_SOFT
#ifdef CONFIG_SYS_I2C_SOFT
#define CONFIG_SYS_I2C
#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0
#define I2C_DELAY              udelay(5)       /* 1/4 I2C clock duration */
#endif

/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
3f0606ad	1	/*
a187559e	2	* U-Boot - Configuration file for BF533 EZKIT board
3f0606ad AL	3	*/
3f0606ad AL	4
cf6f469e MF	5	#ifndef __CONFIG_BF533_EZKIT_H__
cf6f469e MF	6	#define __CONFIG_BF533_EZKIT_H__
3f0606ad	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
cf6f469e MF	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf533-0.3
cf6f469e	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
3f0606ad	15
cf6f469e MF	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 27000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 22
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 5
3f0606ad	38
cf6f469e MF	39	/*
	40	* Memory Settings
	41	*/
	42	#define CONFIG_MEM_SIZE 32
	43	/* Early EZKITs had 32megs, but later have 64megs */
	44	#if (CONFIG_MEM_SIZE == 64)
	45	# define CONFIG_MEM_ADD_WDTH 10
3f0606ad	46	#else
cf6f469e	47	# define CONFIG_MEM_ADD_WDTH 9
3f0606ad AL	48	#endif
3f0606ad AL	49
cf6f469e MF	50	#define CONFIG_EBIU_SDRRC_VAL 0x398
cf6f469e MF	51	#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
3f0606ad	52
cf6f469e MF	53	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	54	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	55	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
3f0606ad	56
cf6f469e MF	57	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
cf6f469e MF	58	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
3f0606ad	59
079a136c	60	/*
cf6f469e	61	* Network Settings
079a136c	62	*/
cf6f469e	63	#define ADI_CMDS_NETWORK 1
7194ab80	64	#define CONFIG_SMC91111 1
cf6f469e MF	65	#define CONFIG_SMC91111_BASE 0x20310300
	66	#define SMC91111_EEPROM_INIT() \
	67	do { \
7194ab80 BW	68	bfin_write_FIO_DIR(bfin_read_FIO_DIR() \| PF1 \| PF0); \
	69	bfin_write_FIO_FLAG_C(PF1); \
	70	bfin_write_FIO_FLAG_S(PF0); \
cf6f469e MF	71	SSYNC(); \
	72	} while (0)
	73	#define CONFIG_HOSTNAME bf533-ezkit
079a136c	74
ba2351f9	75	/*
cf6f469e	76	* Flash Settings
ba2351f9	77	*/
6d0f6bcf	78	#define CONFIG_SYS_FLASH_BASE 0x20000000
cf6f469e MF	79	#define CONFIG_SYS_MAX_FLASH_BANKS 3
	80	#define CONFIG_SYS_MAX_FLASH_SECT 40
	81	#define CONFIG_ENV_IS_IN_FLASH
4c5f307d	82	#define CONFIG_ENV_ADDR 0x20030000
cf6f469e	83	#define CONFIG_ENV_SECT_SIZE 0x10000
3f0606ad	84	#define FLASH_TOT_SECT 40
3f0606ad	85
3f0606ad	86	/*
cf6f469e	87	* I2C Settings
3f0606ad	88	*/
ea818dbb HS	89	#define CONFIG_SYS_I2C_SOFT
	90	#ifdef CONFIG_SYS_I2C_SOFT
	91	#define CONFIG_SYS_I2C
beb60e77 MF	92	#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
beb60e77 MF	93	#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
ea818dbb HS	94	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
	95	#define CONFIG_SYS_I2C_SOFT_SLAVE 0
	96	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	97	#endif
3f0606ad	98
cf6f469e MF	99	/*
	100	* Misc Settings
	101	*/
	102	#define CONFIG_MISC_INIT_R
	103	#define CONFIG_RTC_BFIN
	104	#define CONFIG_UART_CONSOLE 0
9171fc81	105
cf6f469e MF	106	/*
	107	* Pull in common ADI header for remaining command/environment setup
	108	*/
	109	#include <configs/bfin_adi_common.h>
9171fc81	110
3f0606ad	111	#endif