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Blackfin: move CONFIG_BFIN_CPU back to board config.h
[people/ms/u-boot.git] / include / configs / bf533-ezkit.h
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1/*
2 * U-boot - Configuration file for BF533 EZKIT board
3 */
4
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5#ifndef __CONFIG_BF533_EZKIT_H__
6#define __CONFIG_BF533_EZKIT_H__
3f0606ad 7
f348ab85 8#include <asm/config-pre.h>
f7ce12cb 9
3f0606ad 10
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11/*
12 * Processor Settings
13 */
fbcf8e8c 14#define CONFIG_BFIN_CPU bf533-0.3
cf6f469e 15#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
3f0606ad 16
3f0606ad 17
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18/*
19 * Clock Settings
20 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
21 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
22 */
23/* CONFIG_CLKIN_HZ is any value in Hz */
24#define CONFIG_CLKIN_HZ 27000000
25/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
26/* 1 = CLKIN / 2 */
27#define CONFIG_CLKIN_HALF 0
28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
29/* 1 = bypass PLL */
30#define CONFIG_PLL_BYPASS 0
31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
32/* Values can range from 0-63 (where 0 means 64) */
33#define CONFIG_VCO_MULT 22
34/* CCLK_DIV controls the core clock divider */
35/* Values can be 1, 2, 4, or 8 ONLY */
36#define CONFIG_CCLK_DIV 1
37/* SCLK_DIV controls the system clock divider */
38/* Values can range from 1-15 */
39#define CONFIG_SCLK_DIV 5
3f0606ad 40
3f0606ad 41
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42/*
43 * Memory Settings
44 */
45#define CONFIG_MEM_SIZE 32
46/* Early EZKITs had 32megs, but later have 64megs */
47#if (CONFIG_MEM_SIZE == 64)
48# define CONFIG_MEM_ADD_WDTH 10
3f0606ad 49#else
cf6f469e 50# define CONFIG_MEM_ADD_WDTH 9
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51#endif
52
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53#define CONFIG_EBIU_SDRRC_VAL 0x398
54#define CONFIG_EBIU_SDGCTL_VAL 0x91118d
3f0606ad 55
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56#define CONFIG_EBIU_AMGCTL_VAL 0xFF
57#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
58#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
3f0606ad 59
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60#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
61#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
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62
63
079a136c 64/*
cf6f469e 65 * Network Settings
079a136c 66 */
cf6f469e 67#define ADI_CMDS_NETWORK 1
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68#define CONFIG_NET_MULTI
69#define CONFIG_SMC91111 1
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70#define CONFIG_SMC91111_BASE 0x20310300
71#define SMC91111_EEPROM_INIT() \
72 do { \
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73 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
74 bfin_write_FIO_FLAG_C(PF1); \
75 bfin_write_FIO_FLAG_S(PF0); \
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76 SSYNC(); \
77 } while (0)
78#define CONFIG_HOSTNAME bf533-ezkit
79/* Uncomment next line to use fixed MAC address */
80/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
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81
82
ba2351f9 83/*
cf6f469e 84 * Flash Settings
ba2351f9 85 */
6d0f6bcf 86#define CONFIG_SYS_FLASH_BASE 0x20000000
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87#define CONFIG_SYS_MAX_FLASH_BANKS 3
88#define CONFIG_SYS_MAX_FLASH_SECT 40
89#define CONFIG_ENV_IS_IN_FLASH
4c5f307d 90#define CONFIG_ENV_ADDR 0x20030000
cf6f469e 91#define CONFIG_ENV_SECT_SIZE 0x10000
3f0606ad 92#define FLASH_TOT_SECT 40
3f0606ad 93
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94
95/*
cf6f469e 96 * I2C Settings
3f0606ad 97 */
cf6f469e 98#define CONFIG_SOFT_I2C
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99#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF0
100#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF1
3f0606ad 101
3f0606ad 102
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103/*
104 * Misc Settings
105 */
106#define CONFIG_MISC_INIT_R
107#define CONFIG_RTC_BFIN
108#define CONFIG_UART_CONSOLE 0
109
9171fc81 110
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111/*
112 * Pull in common ADI header for remaining command/environment setup
113 */
114#include <configs/bfin_adi_common.h>
9171fc81 115
3f0606ad 116#endif