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Commit | Line | Data |
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3f0606ad | 1 | /* |
a187559e | 2 | * U-Boot - Configuration file for BF533 STAMP board |
3f0606ad AL |
3 | */ |
4 | ||
cf6f469e MF |
5 | #ifndef __CONFIG_BF533_STAMP_H__ |
6 | #define __CONFIG_BF533_STAMP_H__ | |
3f0606ad | 7 | |
f348ab85 | 8 | #include <asm/config-pre.h> |
f7ce12cb | 9 | |
3f0606ad | 10 | /* |
cf6f469e | 11 | * Processor Settings |
3f0606ad | 12 | */ |
fbcf8e8c | 13 | #define CONFIG_BFIN_CPU bf533-0.3 |
cf6f469e | 14 | #define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS |
3f0606ad | 15 | |
3f0606ad | 16 | /* |
cf6f469e MF |
17 | * Clock Settings |
18 | * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV | |
19 | * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV | |
3f0606ad | 20 | */ |
cf6f469e MF |
21 | /* CONFIG_CLKIN_HZ is any value in Hz */ |
22 | #define CONFIG_CLKIN_HZ 11059200 | |
23 | /* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */ | |
24 | /* 1 = CLKIN / 2 */ | |
25 | #define CONFIG_CLKIN_HALF 0 | |
26 | /* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */ | |
27 | /* 1 = bypass PLL */ | |
28 | #define CONFIG_PLL_BYPASS 0 | |
29 | /* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */ | |
30 | /* Values can range from 0-63 (where 0 means 64) */ | |
9f64ba24 | 31 | #define CONFIG_VCO_MULT 45 |
cf6f469e MF |
32 | /* CCLK_DIV controls the core clock divider */ |
33 | /* Values can be 1, 2, 4, or 8 ONLY */ | |
34 | #define CONFIG_CCLK_DIV 1 | |
35 | /* SCLK_DIV controls the system clock divider */ | |
36 | /* Values can range from 1-15 */ | |
baf35705 | 37 | #define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */ |
3f0606ad | 38 | |
3f0606ad | 39 | /* |
cf6f469e | 40 | * Memory Settings |
3f0606ad | 41 | */ |
cf6f469e MF |
42 | #define CONFIG_MEM_ADD_WDTH 11 |
43 | #define CONFIG_MEM_SIZE 128 | |
3f0606ad | 44 | |
cf6f469e MF |
45 | #define CONFIG_EBIU_SDRRC_VAL 0x268 |
46 | #define CONFIG_EBIU_SDGCTL_VAL 0x911109 | |
3f0606ad | 47 | |
cf6f469e MF |
48 | #define CONFIG_EBIU_AMGCTL_VAL 0xFF |
49 | #define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3 | |
50 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983 | |
3f0606ad | 51 | |
cf6f469e MF |
52 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) |
53 | #define CONFIG_SYS_MALLOC_LEN (384 * 1024) | |
3f0606ad | 54 | |
3f0606ad | 55 | /* |
cf6f469e | 56 | * Network Settings |
3f0606ad | 57 | */ |
cf6f469e | 58 | #define ADI_CMDS_NETWORK 1 |
7194ab80 | 59 | #define CONFIG_SMC91111 1 |
cf6f469e MF |
60 | #define CONFIG_SMC91111_BASE 0x20300300 |
61 | #define SMC91111_EEPROM_INIT() \ | |
62 | do { \ | |
7194ab80 BW |
63 | bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \ |
64 | bfin_write_FIO_FLAG_C(PF1); \ | |
65 | bfin_write_FIO_FLAG_S(PF0); \ | |
cf6f469e MF |
66 | SSYNC(); \ |
67 | } while (0) | |
68 | #define CONFIG_HOSTNAME bf533-stamp | |
3f0606ad | 69 | |
ea818dbb HS |
70 | /* I2C */ |
71 | #define CONFIG_SYS_I2C | |
72 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ | |
73 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
74 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
75 | /* | |
76 | * Software (bit-bang) I2C driver configuration | |
77 | */ | |
e5cb60a0 SZ |
78 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
79 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb | 80 | |
3f0606ad | 81 | /* |
cf6f469e | 82 | * Flash Settings |
3f0606ad | 83 | */ |
cf6f469e MF |
84 | #define CONFIG_FLASH_CFI_DRIVER |
85 | #define CONFIG_SYS_FLASH_BASE 0x20000000 | |
86 | #define CONFIG_SYS_FLASH_CFI | |
87 | #define CONFIG_SYS_FLASH_CFI_AMD_RESET | |
88 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
89 | #define CONFIG_SYS_MAX_FLASH_SECT 67 | |
3f0606ad | 90 | |
079a136c | 91 | /* |
cf6f469e | 92 | * SPI Settings |
079a136c | 93 | */ |
cf6f469e MF |
94 | #define CONFIG_BFIN_SPI |
95 | #define CONFIG_ENV_SPI_MAX_HZ 30000000 | |
c49eabef | 96 | /* |
afac8b07 | 97 | #define CONFIG_SF_DEFAULT_SPEED 30000000 |
f453220c | 98 | #define CONFIG_SPI_FLASH_ALL |
c49eabef | 99 | */ |
079a136c | 100 | |
ba2351f9 | 101 | /* |
cf6f469e | 102 | * Env Storage Settings |
ba2351f9 | 103 | */ |
cf6f469e MF |
104 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) |
105 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
bc43a8d8 | 106 | #define CONFIG_ENV_OFFSET 0x10000 |
cf6f469e | 107 | #define CONFIG_ENV_SIZE 0x2000 |
bc43a8d8 | 108 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
cf6f469e MF |
109 | #else |
110 | #define CONFIG_ENV_IS_IN_FLASH | |
111 | #define CONFIG_ENV_OFFSET 0x4000 | |
112 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET) | |
113 | #define CONFIG_ENV_SIZE 0x2000 | |
114 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
ba2351f9 | 115 | #endif |
cf6f469e MF |
116 | #if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS) |
117 | #define ENV_IS_EMBEDDED | |
3f0606ad | 118 | #else |
76d82187 | 119 | #define CONFIG_ENV_IS_EMBEDDED_IN_LDR |
3f0606ad | 120 | #endif |
9ff67e5e MF |
121 | #ifdef ENV_IS_EMBEDDED |
122 | /* WARNING - the following is hand-optimized to fit within | |
123 | * the sector before the environment sector. If it throws | |
124 | * an error during compilation remove an object here to get | |
125 | * it linked after the configuration sector. | |
126 | */ | |
127 | # define LDS_BOARD_TEXT \ | |
e2906a59 MY |
128 | arch/blackfin/lib/built-in.o (.text*); \ |
129 | arch/blackfin/cpu/built-in.o (.text*); \ | |
9ff67e5e | 130 | . = DEFINED(env_offset) ? env_offset : .; \ |
c70e7ddb | 131 | common/env_embedded.o (.text*); |
9ff67e5e | 132 | #endif |
3f0606ad | 133 | |
3f0606ad | 134 | /* |
cf6f469e | 135 | * I2C Settings |
3f0606ad | 136 | */ |
ea818dbb HS |
137 | #define CONFIG_SYS_I2C_SOFT |
138 | #ifdef CONFIG_SYS_I2C_SOFT | |
139 | #define CONFIG_SYS_I2C | |
beb60e77 MF |
140 | #define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3 |
141 | #define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2 | |
ea818dbb HS |
142 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ |
143 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
144 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0 | |
145 | #endif | |
3f0606ad AL |
146 | |
147 | /* | |
cf6f469e | 148 | * Compact Flash / IDE / ATA Settings |
3f0606ad AL |
149 | */ |
150 | ||
151 | /* Enabled below option for CF support */ | |
cf6f469e MF |
152 | /* #define CONFIG_STAMP_CF */ |
153 | #if defined(CONFIG_STAMP_CF) | |
154 | #define CONFIG_MISC_INIT_R | |
8db13d63 AL |
155 | #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ |
156 | #undef CONFIG_IDE_LED /* no led for ide supported */ | |
157 | #undef CONFIG_IDE_RESET /* no reset for ide supported */ | |
3f0606ad | 158 | |
cf6f469e MF |
159 | #define CONFIG_SYS_IDE_MAXBUS 1 |
160 | #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1) | |
3f0606ad | 161 | |
6d0f6bcf JCPV |
162 | #define CONFIG_SYS_ATA_BASE_ADDR 0x20200000 |
163 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
3f0606ad | 164 | |
cf6f469e MF |
165 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */ |
166 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */ | |
167 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */ | |
3f0606ad | 168 | |
6d0f6bcf | 169 | #define CONFIG_SYS_ATA_STRIDE 2 |
cf6f469e MF |
170 | |
171 | #undef CONFIG_EBIU_AMBCTL1_VAL | |
172 | #define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2 | |
3f0606ad AL |
173 | #endif |
174 | ||
175 | /* | |
cf6f469e | 176 | * Misc Settings |
3f0606ad | 177 | */ |
cf6f469e MF |
178 | #define CONFIG_RTC_BFIN |
179 | #define CONFIG_UART_CONSOLE 0 | |
3f0606ad | 180 | |
cf6f469e MF |
181 | /* FLASH/ETHERNET uses the same async bank */ |
182 | #define SHARED_RESOURCES 1 | |
3f0606ad | 183 | |
23fd959e MF |
184 | /* define to enable boot progress via leds */ |
185 | /* #define CONFIG_SHOW_BOOT_PROGRESS */ | |
186 | ||
187 | /* define to enable run status via led */ | |
23fd959e | 188 | |
cf6f469e | 189 | /* define to enable splash screen support */ |
3f0606ad | 190 | |
3f0606ad | 191 | /* |
cf6f469e | 192 | * Pull in common ADI header for remaining command/environment setup |
3f0606ad | 193 | */ |
cf6f469e | 194 | #include <configs/bfin_adi_common.h> |
9171fc81 | 195 | |
3f0606ad | 196 | #endif |