[people/ms/u-boot.git] / include / configs / bf533-stamp.h

/*
 * U-boot - Configuration file for BF533 STAMP board
 */

#ifndef __CONFIG_STAMP_H__
#define __CONFIG_STAMP_H__

#include <asm/blackfin-config-pre.h>

#define CONFIG_STAMP			1
#define CONFIG_RTC_BFIN			1
#define CONFIG_BF533			1
/*
 * Boot Mode Set
 * Blackfin can support several boot modes
 */
#define BF533_BYPASS_BOOT	0x0001	/* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
#define BF533_PARA_BOOT		0x0002	/* Bootmode 1: Boot from 8-bit or 16-bit flash */
#define BF533_SPI_BOOT		0x0004	/* Bootmode 3: Boot from SPI flash */
/* Define the boot mode */
#define BFIN_BOOT_MODE		BF533_BYPASS_BOOT
/* #define BFIN_BOOT_MODE	BF533_SPI_BOOT */

#define CONFIG_PANIC_HANG 1

#define CONFIG_BFIN_CPU	bf533-0.3

/* This sets the default state of the cache on U-Boot's boot */
#define CONFIG_ICACHE_ON
#define CONFIG_DCACHE_ON

/* Define where the uboot will be loaded by on-chip boot rom */
#define APP_ENTRY 0x00001000

/*
 * Stringize definitions - needed for environmental settings
 */
#define STRINGIZE2(x) #x
#define STRINGIZE(x) STRINGIZE2(x)

/*
 * Board settings
 */
#define CONFIG_DRIVER_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20300300

/* FLASH/ETHERNET uses the same address range */
#define SHARED_RESOURCES 	1

/* Is I2C bit-banged? */
#define CONFIG_SOFT_I2C		1

/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL			PF3
#define PF_SDA			PF2

/*
 * Video splash screen support
 */
#define  CONFIG_VIDEO		0

#define CONFIG_VDSP		1

/*
 * Clock settings
 */

/* CONFIG_CLKIN_HZ is any value in Hz				*/
#define CONFIG_CLKIN_HZ		11059200
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	*/
/*						    1=CLKIN/2	*/
#define CONFIG_CLKIN_HALF	0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	*/
/*						 1=bypass PLL	*/
#define CONFIG_PLL_BYPASS	0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	*/
/* Values can range from 1-64					*/
#define CONFIG_VCO_MULT		36
/* CONFIG_CCLK_DIV controls what the core clock divider is	*/
/* Values can be 1, 2, 4, or 8 ONLY				*/
#define CONFIG_CCLK_DIV		1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
/* Values can range from 1-15					*/
#define CONFIG_SCLK_DIV		5
/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider	*/
/* Values can range from 2-65535				*/
/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD)			*/
#define CONFIG_SPI_BAUD		2

#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_SPI_BAUD_INITBLOCK	4
#endif

/*
 * Network settings
 */

#if (CONFIG_DRIVER_SMC91111)
#if 0
#define	CONFIG_MII
#endif

/* network support */
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		STAMP
#define CONFIG_ROOTPATH		/checkout/uClinux-dist/romfs

/* To remove hardcoding and enable MAC storage in EEPROM  */
/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */
#endif /* CONFIG_DRIVER_SMC91111 */

/*
 * Flash settings
 */

#define CFG_FLASH_CFI		/* The flash is CFI compatible  */
#define CFG_FLASH_CFI_DRIVER	/* Use common CFI driver	*/
#define	CFG_FLASH_CFI_AMD_RESET

#define CFG_FLASH_BASE		0x20000000
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CFG_MAX_FLASH_SECT	67	/* max number of sectors on one chip */

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_ADDR		0x20004000
#define	CFG_ENV_OFFSET		(CFG_ENV_ADDR - CFG_FLASH_BASE)
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CFG_ENV_IS_IN_EEPROM	1
#define CFG_ENV_OFFSET		0x4000
#define CFG_ENV_HEADER		(CFG_ENV_OFFSET + 0x12A)	/* 0x12A is the length of LDR file header */
#endif

#define	CFG_ENV_SIZE		0x2000
#define CFG_ENV_SECT_SIZE 	0x2000	/* Total Size of Environment Sector */
#define	ENV_IS_EMBEDDED

#define CFG_FLASH_ERASE_TOUT	30000	/* Timeout for Chip Erase (in ms) */
#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT	1	/* Timeout for Flash Write (in ms) */

/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS  1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR 	11

/*
 * following timeouts shall be used once the
 * Flash real protection is enabled
 */
#define CFG_FLASH_LOCK_TOUT	5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT	10000	/* Timeout for Flash Clear Lock Bits (in ms) */

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE		128	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH     11	/* 8, 9, 10, 11    */
#define CONFIG_MEM_MT48LC64M4A2FB_7E	1

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_MEMTEST_START	0x00000000	/* memtest works on */
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CFG_MEMTEST_START	0x00100000	/* memtest works on */
#endif

#define	CFG_SDRAM_BASE		0x00000000

#define CFG_MAX_RAM_SIZE	(CONFIG_MEM_SIZE * 1024 *1024)
#define CFG_MEMTEST_END		(CFG_MAX_RAM_SIZE - 0x80000 - 1)
#define CONFIG_LOADADDR		0x01000000

#define CFG_LOAD_ADDR 		CONFIG_LOADADDR
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 << 10)     /* Reserve 128 kB for malloc()	*/
#define CFG_GBL_DATA_SIZE	0x4000		/* Reserve 16k for Global Data  */
#define CONFIG_STACKSIZE	(128*1024)	/* regular stack */

#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - 0x40000)
#define CFG_MALLOC_BASE		(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_ADDR	(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE	(CFG_GBL_DATA_ADDR  - 4)

/* Check to make sure everything fits in SDRAM */
#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	#error Memory Map does not fit into configuration
#endif

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ		( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ		(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ		( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ		( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ		CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ		CONFIG_CLKIN_HZ
#endif

#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
#else
#undef CONFIG_SPI_FLASH_FAST_READ
#endif
#endif

/*
 * Command settings
 */

#define CFG_LONGHELP		1
#define CONFIG_CMDLINE_EDITING	1

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CFG_AUTOLOAD		"no"	/*rarpb, bootp or dhcp commands will perform only a */
#endif

/* configuration lookup from the BOOTP/DHCP server, */
/* but not try to load any image using TFTP	    */

#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOT_RETRY_TIME	-1	/* Enable this if bootretry required, currently its disabled */
#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_BOOTCOMMAND	"run ramboot"
#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_BOOTCOMMAND 	"eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
#endif

#define CONFIG_BOOTARGS		"root=/dev/mtdblock0 rw console=ttyBF0,57600"


#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
		"$(rootpath) console=ttyBF0,57600\0" \
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux; " \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux; " \
		"run nfsargs;run addip;bootelf\0" \
	"flashboot=bootm 0x20100000\0" \
	"update=tftpboot $(loadaddr) u-boot.bin; " \
		"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
		"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	""
#else
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"flashboot=bootm 0x20100000\0" \
	"
#endif

#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
		"$(rootpath) console=ttyBF0,57600\0"	\
	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
		"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	"ramboot=tftpboot $(loadaddr) linux; " \
		"run ramargs;run addip;bootelf\0" \
	"nfsboot=tftpboot $(loadaddr) linux; "	\
		"run nfsargs;run addip;bootelf\0" \
	"flashboot=bootm 0x20100000\0" \
	"update=tftpboot $(loadaddr) u-boot.ldr;"	\
		"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
	""
#endif

#ifdef CONFIG_SOFT_I2C
#if (!CONFIG_SOFT_I2C)
#undef CONFIG_SOFT_I2C
#endif
#endif


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_DATE

#if (CONFIG_DRIVER_SMC91111)
#define CONFIG_CMD_PING
#endif

#if (CONFIG_SOFT_I2C)
#define CONFIG_CMD_I2C
#endif

#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
#define CONFIG_CMD_DHCP
#endif


/*
 * Console settings
 */

#define CONFIG_BAUDRATE		57600
#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

#define	CFG_PROMPT		"bfin> "	/* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE	(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_LOADS_ECHO	1

/*
 * I2C settings
 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
 */
#if (CONFIG_SOFT_I2C)

#define I2C_INIT		(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE		(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE		(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ		((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SDA; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SDA; \
				asm("ssync;"); \
				}
#define I2C_SCL(bit)	if(bit) { \
				*pFIO_FLAG_S = PF_SCL; \
				asm("ssync;"); \
				} \
			else	{ \
				*pFIO_FLAG_C = PF_SCL; \
				asm("ssync;"); \
				}
#define I2C_DELAY		udelay(5)	/* 1/4 I2C clock duration */

#define CFG_I2C_SPEED		50000
#define CFG_I2C_SLAVE		0xFE
#endif /* CONFIG_SOFT_I2C */

/*
 * Compact Flash settings
 */

/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF	1 */

#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)

#define CONFIG_MISC_INIT_R	1
#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef  CONFIG_IDE_LED			/* no led for ide supported */
#undef  CONFIG_IDE_RESET		/* no reset for ide supported */

#define CFG_IDE_MAXBUS		1	/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	0x20200000
#define CFG_ATA_IDE0_OFFSET	0x0000

#define CFG_ATA_DATA_OFFSET	0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET	0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET	0x0007	/* Offset for alternate registers */

#define CFG_ATA_STRIDE		2
#endif

/*
 * Miscellaneous configurable options
 */

#define	CFG_HZ			1000	/* 1ms time tick */

#define CFG_BOOTM_LEN		0x4000000/* Large Image Length, set to 64 Meg */

#define CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs */

#define CONFIG_SPI

#ifdef  CONFIG_VIDEO
#if (CONFIG_VIDEO)
#define CONFIG_SPLASH_SCREEN	1
#define CONFIG_SILENT_CONSOLE	1
#else
#undef CONFIG_VIDEO
#endif
#endif

/*
 * FLASH organization and environment definitions
 */
#define	CFG_BOOTMAPSZ		(8 << 20)/* Initial Memory map for Linux */

/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL | \
				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
#define AMBCTL1VAL   		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL | \
				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
*/
#define AMGCTLVAL		0xFF
#define AMBCTL0VAL		0xBBC3BBC3
#define AMBCTL1VAL		0x99B39983
#define CF_AMBCTL1VAL		0x99B3ffc2

#ifdef CONFIG_VDSP
#define ET_EXEC_VDSP		0x8
#define SHT_STRTAB_VDSP		0x1
#define ELFSHDRSIZE_VDSP	0x2C
#define VDSP_ENTRY_ADDR		0xFFA00000
#endif

#endif
Commit	Line	Data
3f0606ad AL	1	/*
	2	* U-boot - Configuration file for BF533 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_STAMP_H__
	6	#define __CONFIG_STAMP_H__
	7
f7ce12cb MF	8	#include <asm/blackfin-config-pre.h>
f7ce12cb MF	9
3f0606ad AL	10	#define CONFIG_STAMP 1
	11	#define CONFIG_RTC_BFIN 1
	12	#define CONFIG_BF533 1
	13	/*
	14	* Boot Mode Set
	15	* Blackfin can support several boot modes
	16	*/
8db13d63 AL	17	#define BF533_BYPASS_BOOT 0x0001 /* Bootmode 0: Execute from 16-bit externeal memory ( bypass BOOT ROM) */
	18	#define BF533_PARA_BOOT 0x0002 /* Bootmode 1: Boot from 8-bit or 16-bit flash */
	19	#define BF533_SPI_BOOT 0x0004 /* Bootmode 3: Boot from SPI flash */
3f0606ad AL	20	/* Define the boot mode */
3f0606ad AL	21	#define BFIN_BOOT_MODE BF533_BYPASS_BOOT
8db13d63	22	/* #define BFIN_BOOT_MODE BF533_SPI_BOOT */
3f0606ad AL	23
	24	#define CONFIG_PANIC_HANG 1
	25
f7ce12cb	26	#define CONFIG_BFIN_CPU bf533-0.3
3f0606ad AL	27
	28	/* This sets the default state of the cache on U-Boot's boot */
	29	#define CONFIG_ICACHE_ON
	30	#define CONFIG_DCACHE_ON
	31
	32	/* Define where the uboot will be loaded by on-chip boot rom */
	33	#define APP_ENTRY 0x00001000
	34
	35	/*
	36	* Stringize definitions - needed for environmental settings
	37	*/
	38	#define STRINGIZE2(x) #x
	39	#define STRINGIZE(x) STRINGIZE2(x)
	40
	41	/*
	42	* Board settings
3f0606ad	43	*/
8db13d63 AL	44	#define CONFIG_DRIVER_SMC91111 1
8db13d63 AL	45	#define CONFIG_SMC91111_BASE 0x20300300
3f0606ad AL	46
3f0606ad AL	47	/* FLASH/ETHERNET uses the same address range */
8db13d63	48	#define SHARED_RESOURCES 1
3f0606ad AL	49
3f0606ad AL	50	/* Is I2C bit-banged? */
8db13d63	51	#define CONFIG_SOFT_I2C 1
3f0606ad AL	52
	53	/*
	54	* Software (bit-bang) I2C driver configuration
	55	*/
8db13d63 AL	56	#define PF_SCL PF3
8db13d63 AL	57	#define PF_SDA PF2
3f0606ad AL	58
	59	/*
	60	* Video splash screen support
	61	*/
8db13d63	62	#define CONFIG_VIDEO 0
3f0606ad	63
8db13d63	64	#define CONFIG_VDSP 1
3f0606ad AL	65
	66	/*
	67	* Clock settings
3f0606ad AL	68	*/
3f0606ad AL	69
8db13d63 AL	70	/* CONFIG_CLKIN_HZ is any value in Hz */
	71	#define CONFIG_CLKIN_HZ 11059200
	72	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
	73	/* 1=CLKIN/2 */
	74	#define CONFIG_CLKIN_HALF 0
	75	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	76	/* 1=bypass PLL */
	77	#define CONFIG_PLL_BYPASS 0
	78	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	79	/* Values can range from 1-64 */
	80	#define CONFIG_VCO_MULT 36
	81	/* CONFIG_CCLK_DIV controls what the core clock divider is */
	82	/* Values can be 1, 2, 4, or 8 ONLY */
	83	#define CONFIG_CCLK_DIV 1
	84	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is*/
	85	/* Values can range from 1-15 */
	86	#define CONFIG_SCLK_DIV 5
	87	/* CONFIG_SPI_BAUD controls the SPI peripheral clock divider */
	88	/* Values can range from 2-65535 */
	89	/* SCK Frequency = SCLK / (2 * CONFIG_SPI_BAUD) */
	90	#define CONFIG_SPI_BAUD 2
3f0606ad AL	91
3f0606ad AL	92	#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	93	#define CONFIG_SPI_BAUD_INITBLOCK 4
3f0606ad AL	94	#endif
3f0606ad AL	95
3f0606ad AL	96	/*
3f0606ad AL	97	* Network settings
3f0606ad AL	98	*/
	99
	100	#if (CONFIG_DRIVER_SMC91111)
	101	#if 0
	102	#define CONFIG_MII
	103	#endif
	104
	105	/* network support */
8db13d63 AL	106	#define CONFIG_IPADDR 192.168.0.15
	107	#define CONFIG_NETMASK 255.255.255.0
	108	#define CONFIG_GATEWAYIP 192.168.0.1
	109	#define CONFIG_SERVERIP 192.168.0.2
	110	#define CONFIG_HOSTNAME STAMP
	111	#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
3f0606ad AL	112
3f0606ad AL	113	/* To remove hardcoding and enable MAC storage in EEPROM */
8db13d63	114	/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
3f0606ad AL	115	#endif /* CONFIG_DRIVER_SMC91111 */
	116
	117	/*
	118	* Flash settings
3f0606ad AL	119	*/
3f0606ad AL	120
8db13d63	121	#define CFG_FLASH_CFI /* The flash is CFI compatible */
0d93de11	122	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
3f0606ad AL	123	#define CFG_FLASH_CFI_AMD_RESET
3f0606ad AL	124
8db13d63 AL	125	#define CFG_FLASH_BASE 0x20000000
	126	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	127	#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
3f0606ad AL	128
3f0606ad AL	129	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63 AL	130	#define CFG_ENV_IS_IN_FLASH 1
	131	#define CFG_ENV_ADDR 0x20004000
	132	#define CFG_ENV_OFFSET (CFG_ENV_ADDR - CFG_FLASH_BASE)
3f0606ad	133	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63 AL	134	#define CFG_ENV_IS_IN_EEPROM 1
	135	#define CFG_ENV_OFFSET 0x4000
	136	#define CFG_ENV_HEADER (CFG_ENV_OFFSET + 0x12A) /* 0x12A is the length of LDR file header */
3f0606ad AL	137	#endif
3f0606ad AL	138
8db13d63 AL	139	#define CFG_ENV_SIZE 0x2000
8db13d63 AL	140	#define CFG_ENV_SECT_SIZE 0x2000 /* Total Size of Environment Sector */
3f0606ad AL	141	#define ENV_IS_EMBEDDED
3f0606ad AL	142
8db13d63	143	#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
3f0606ad	144	#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
8db13d63	145	#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
3f0606ad AL	146
	147	/* JFFS Partition offset set */
	148	#define CFG_JFFS2_FIRST_BANK 0
	149	#define CFG_JFFS2_NUM_BANKS 1
	150	/* 512k reserved for u-boot */
8db13d63	151	#define CFG_JFFS2_FIRST_SECTOR 11
3f0606ad AL	152
	153	/*
	154	* following timeouts shall be used once the
	155	* Flash real protection is enabled
	156	*/
8db13d63 AL	157	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
8db13d63 AL	158	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
3f0606ad AL	159
	160	/*
	161	* SDRAM settings & memory map
3f0606ad AL	162	*/
3f0606ad AL	163
8db13d63 AL	164	#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
8db13d63 AL	165	#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
3f0606ad AL	166	#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
	167
	168	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	169	#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
3f0606ad	170	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	171	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
3f0606ad AL	172	#endif
3f0606ad AL	173
8db13d63	174	#define CFG_SDRAM_BASE 0x00000000
3f0606ad AL	175
	176	#define CFG_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 *1024)
	177	#define CFG_MEMTEST_END (CFG_MAX_RAM_SIZE - 0x80000 - 1)
	178	#define CONFIG_LOADADDR 0x01000000
	179
8db13d63 AL	180	#define CFG_LOAD_ADDR CONFIG_LOADADDR
	181	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	182	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	183	#define CFG_GBL_DATA_SIZE 0x4000 /* Reserve 16k for Global Data */
	184	#define CONFIG_STACKSIZE (1281024) / regular stack */
3f0606ad AL	185
3f0606ad AL	186	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - 0x40000)
8db13d63 AL	187	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	188	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	189	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
3f0606ad AL	190
	191	/* Check to make sure everything fits in SDRAM */
	192	#if ((CFG_MONITOR_BASE + CFG_MONITOR_LEN) > CFG_MAX_RAM_SIZE)
	193	#error Memory Map does not fit into configuration
	194	#endif
	195
	196	#if ( CONFIG_CLKIN_HALF == 0 )
8db13d63	197	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
3f0606ad	198	#else
8db13d63	199	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
3f0606ad AL	200	#endif
	201
	202	#if (CONFIG_PLL_BYPASS == 0)
8db13d63 AL	203	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
8db13d63 AL	204	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
3f0606ad	205	#else
8db13d63 AL	206	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
8db13d63 AL	207	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
3f0606ad AL	208	#endif
	209
	210	#if (BFIN_BOOT_MODE == BF533_SPI_BOOT)
	211	#if (CONFIG_SCLK_HZ / (2*CONFIG_SPI_BAUD) > 20000000)
	212	#define CONFIG_SPI_FLASH_FAST_READ 1 /* Needed if SPI_CLK > 20 MHz */
	213	#else
	214	#undef CONFIG_SPI_FLASH_FAST_READ
	215	#endif
	216	#endif
8db13d63	217
3f0606ad AL	218	/*
3f0606ad AL	219	* Command settings
3f0606ad AL	220	*/
3f0606ad AL	221
8db13d63 AL	222	#define CFG_LONGHELP 1
8db13d63 AL	223	#define CONFIG_CMDLINE_EDITING 1
3f0606ad AL	224
3f0606ad AL	225	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	226	#define CFG_AUTOLOAD "no" /rarpb, bootp or dhcp commands will perform only a /
3f0606ad	227	#endif
3f0606ad	228
8db13d63	229	/* configuration lookup from the BOOTP/DHCP server, */
0d93de11	230	/* but not try to load any image using TFTP */
8db13d63 AL	231
	232	#define CONFIG_BOOTDELAY 5
	233	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
3f0606ad	234	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
8db13d63	235	#define CONFIG_BOOTCOMMAND "run ramboot"
3f0606ad	236	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
8db13d63	237	#define CONFIG_BOOTCOMMAND "eeprom read 0x1000000 0x100000 0x180000;icache on;dcache on;bootm 0x1000000"
3f0606ad AL	238	#endif
3f0606ad AL	239
8db13d63	240	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw console=ttyBF0,57600"
3f0606ad	241
3f0606ad AL	242
	243	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
	244	#if (CONFIG_DRIVER_SMC91111)
	245	#define CONFIG_EXTRA_ENV_SETTINGS \
8db13d63 AL	246	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	247	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
	248	"$(rootpath) console=ttyBF0,57600\0" \
	249	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
	250	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
	251	"ramboot=tftpboot $(loadaddr) linux; " \
3f0606ad	252	"run ramargs;run addip;bootelf\0" \
8db13d63	253	"nfsboot=tftpboot $(loadaddr) linux; " \
3f0606ad	254	"run nfsargs;run addip;bootelf\0" \
8db13d63 AL	255	"flashboot=bootm 0x20100000\0" \
	256	"update=tftpboot $(loadaddr) u-boot.bin; " \
	257	"protect off 0x20000000 0x2003FFFF; erase 0x20000000 0x2003FFFF;" \
	258	"cp.b $(loadaddr) 0x20000000 $(filesize)\0" \
	259	""
3f0606ad AL	260	#else
3f0606ad AL	261	#define CONFIG_EXTRA_ENV_SETTINGS \
8db13d63 AL	262	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	263	"flashboot=bootm 0x20100000\0" \
	264	"
3f0606ad AL	265	#endif
	266
	267	#elif (BFIN_BOOT_MODE == BF533_SPI_BOOT)
	268	#define CONFIG_EXTRA_ENV_SETTINGS \
	269	"ramargs=setenv bootargs root=/dev/mtdblock0 rw console=ttyBF0,57600\0" \
	270	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):" \
	271	"$(rootpath) console=ttyBF0,57600\0" \
	272	"addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \
	273	"$(gatewayip):$(netmask):$(hostname):eth0:off\0" \
0d93de11	274	"ramboot=tftpboot $(loadaddr) linux; " \
3f0606ad AL	275	"run ramargs;run addip;bootelf\0" \
	276	"nfsboot=tftpboot $(loadaddr) linux; " \
	277	"run nfsargs;run addip;bootelf\0" \
	278	"flashboot=bootm 0x20100000\0" \
	279	"update=tftpboot $(loadaddr) u-boot.ldr;" \
	280	"eeprom write $(loadaddr) 0x0 $(filesize);\0"\
	281	""
	282	#endif
	283
	284	#ifdef CONFIG_SOFT_I2C
	285	#if (!CONFIG_SOFT_I2C)
	286	#undef CONFIG_SOFT_I2C
	287	#endif
	288	#endif
	289
ba2351f9	290
079a136c JL	291	/*
	292	* BOOTP options
	293	*/
	294	#define CONFIG_BOOTP_BOOTFILESIZE
	295	#define CONFIG_BOOTP_BOOTPATH
	296	#define CONFIG_BOOTP_GATEWAY
	297	#define CONFIG_BOOTP_HOSTNAME
	298
	299
ba2351f9 JL	300	/*
	301	* Command line configuration.
	302	*/
	303	#include <config_cmd_default.h>
	304
	305	#define CONFIG_CMD_ELF
	306	#define CONFIG_CMD_CACHE
	307	#define CONFIG_CMD_JFFS2
	308	#define CONFIG_CMD_EEPROM
	309	#define CONFIG_CMD_DATE
	310
	311	#if (CONFIG_DRIVER_SMC91111)
	312	#define CONFIG_CMD_PING
	313	#endif
	314
3f0606ad	315	#if (CONFIG_SOFT_I2C)
ba2351f9 JL	316	#define CONFIG_CMD_I2C
ba2351f9 JL	317	#endif
3f0606ad AL	318
3f0606ad AL	319	#if (BFIN_BOOT_MODE == BF533_BYPASS_BOOT)
ba2351f9	320	#define CONFIG_CMD_DHCP
3f0606ad AL	321	#endif
3f0606ad AL	322
3f0606ad AL	323
	324	/*
	325	* Console settings
3f0606ad AL	326	*/
3f0606ad AL	327
8db13d63 AL	328	#define CONFIG_BAUDRATE 57600
8db13d63 AL	329	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3f0606ad	330
f7ce12cb	331	#define CFG_PROMPT "bfin> " /* Monitor Command Prompt */
3f0606ad	332
ba2351f9	333	#if defined(CONFIG_CMD_KGDB)
8db13d63	334	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
3f0606ad	335	#else
8db13d63	336	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
3f0606ad	337	#endif
8db13d63 AL	338	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	339	#define CFG_MAXARGS 16 /* max number of command args */
	340	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
3f0606ad	341
8db13d63	342	#define CONFIG_LOADS_ECHO 1
3f0606ad AL	343
	344	/*
	345	* I2C settings
	346	* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
	347	*/
	348	#if (CONFIG_SOFT_I2C)
	349
8db13d63 AL	350	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	351	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	352	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	353	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	354	#define I2C_SDA(bit) if(bit) { \
	355	*pFIO_FLAG_S = PF_SDA; \
	356	asm("ssync;"); \
	357	} \
	358	else { \
	359	*pFIO_FLAG_C = PF_SDA; \
	360	asm("ssync;"); \
	361	}
	362	#define I2C_SCL(bit) if(bit) { \
	363	*pFIO_FLAG_S = PF_SCL; \
	364	asm("ssync;"); \
	365	} \
	366	else { \
	367	*pFIO_FLAG_C = PF_SCL; \
	368	asm("ssync;"); \
	369	}
	370	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	371
	372	#define CFG_I2C_SPEED 50000
	373	#define CFG_I2C_SLAVE 0xFE
3f0606ad AL	374	#endif /* CONFIG_SOFT_I2C */
	375
	376	/*
	377	* Compact Flash settings
	378	*/
	379
	380	/* Enabled below option for CF support */
8db13d63	381	/* #define CONFIG_STAMP_CF 1 */
3f0606ad	382
ba2351f9	383	#if defined(CONFIG_STAMP_CF) && defined(CONFIG_CMD_IDE)
3f0606ad	384
8db13d63 AL	385	#define CONFIG_MISC_INIT_R 1
8db13d63 AL	386	#define CONFIG_DOS_PARTITION 1
3f0606ad AL	387	/*
	388	* IDE/ATA stuff
	389	*/
8db13d63 AL	390	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	391	#undef CONFIG_IDE_LED /* no led for ide supported */
	392	#undef CONFIG_IDE_RESET /* no reset for ide supported */
3f0606ad	393
8db13d63 AL	394	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
8db13d63 AL	395	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
3f0606ad	396
8db13d63 AL	397	#define CFG_ATA_BASE_ADDR 0x20200000
8db13d63 AL	398	#define CFG_ATA_IDE0_OFFSET 0x0000
3f0606ad	399
8db13d63 AL	400	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	401	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	402	#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
3f0606ad	403
8db13d63	404	#define CFG_ATA_STRIDE 2
3f0606ad AL	405	#endif
	406
	407	/*
	408	* Miscellaneous configurable options
	409	*/
	410
8db13d63	411	#define CFG_HZ 1000 /* 1ms time tick */
3f0606ad	412
8db13d63	413	#define CFG_BOOTM_LEN 0x4000000/* Large Image Length, set to 64 Meg */
3f0606ad	414
8db13d63	415	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
3f0606ad AL	416
	417	#define CONFIG_SPI
	418
	419	#ifdef CONFIG_VIDEO
	420	#if (CONFIG_VIDEO)
8db13d63 AL	421	#define CONFIG_SPLASH_SCREEN 1
8db13d63 AL	422	#define CONFIG_SILENT_CONSOLE 1
3f0606ad AL	423	#else
	424	#undef CONFIG_VIDEO
	425	#endif
	426	#endif
	427
	428	/*
	429	* FLASH organization and environment definitions
	430	*/
8db13d63	431	#define CFG_BOOTMAPSZ (8 << 20)/* Initial Memory map for Linux */
3f0606ad AL	432
3f0606ad AL	433	/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
8db13d63 AL	434	/*#define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)
	435	#define AMBCTL0VAL (B1WAT_11 \| B1RAT_11 \| B1HT_3 \| B1ST_4 \| B1TT_4 \| B1RDYPOL \| \
	436	B1RDYEN \| B0WAT_11 \| B0RAT_11 \| B0HT_3 \| B0ST_4 \| B0TT_4 \| B0RDYPOL \| B0RDYEN)
	437	#define AMBCTL1VAL (B3WAT_9 \| B3RAT_9 \| B3HT_2 \| B3ST_3 \| B3TT_4 \| B3RDYPOL \| \
	438	B3RDYEN \| B2WAT_9 \| B2RAT_9 \| B2HT_2 \| B2ST_4 \| B2TT_4 \| B2RDYPOL \| B2RDYEN)
3f0606ad	439	*/
8db13d63 AL	440	#define AMGCTLVAL 0xFF
	441	#define AMBCTL0VAL 0xBBC3BBC3
	442	#define AMBCTL1VAL 0x99B39983
	443	#define CF_AMBCTL1VAL 0x99B3ffc2
3f0606ad AL	444
	445	#ifdef CONFIG_VDSP
	446	#define ET_EXEC_VDSP 0x8
	447	#define SHT_STRTAB_VDSP 0x1
	448	#define ELFSHDRSIZE_VDSP 0x2C
	449	#define VDSP_ENTRY_ADDR 0xFFA00000
	450	#endif
	451
3f0606ad	452	#endif