[people/ms/u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-Boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_STAMP_H__
#define __CONFIG_BF537_STAMP_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x306
#define CONFIG_EBIU_SDGCTL_VAL	0x91114d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)

/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#endif
#define CONFIG_HOSTNAME		bf537-stamp

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT	71

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_ALL

/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * SPI_MMC Settings
 */
#define CONFIG_MMC_SPI
#ifdef CONFIG_MMC_SPI
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#endif

/*
 * NAND Settings
 */
/* #define CONFIG_NAND_PLAT */
#ifdef CONFIG_NAND_PLAT
#define CONFIG_SYS_NAND_BASE		0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_GPIO_DEV_READY       GPIO_PF3
#endif /* CONFIG_NAND_PLAT */

/*
 * CF-CARD IDE-HDD Support
 */

/*
 * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
 * Strange address mapping Blackfin A13 connects to CF_A0
 */

/* #define CONFIG_BFIN_TRUE_IDE */

/*
 * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
 * This should be the preferred mode
 */

/* #define CONFIG_BFIN_CF_IDE */

/*
 * Add IDE Disk Drive (HDD) support
 * See example interface here:
 * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
 */

/* #define CONFIG_BFIN_HDD_IDE */

#if defined(CONFIG_BFIN_CF_IDE) || \
    defined(CONFIG_BFIN_HDD_IDE) || \
    defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
# define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)

#undef  CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */

#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */

#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif

#endif

/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_SYS_POST_HOTKEYS_GPIO	GPIO_PF5
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	10, 11, 12, 13,
#define CONFIG_SYS_POST_FLASH_START	11
#define CONFIG_SYS_POST_FLASH_END	71
#endif

/* These are for board tests */
#if 0
#define CONFIG_BOOTCOMMAND       "bootldr 0x203f0100"
#endif

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
26bf7dec	1	/*
a187559e	2	* U-Boot - Configuration file for BF537 STAMP board
26bf7dec AL	3	*/
26bf7dec AL	4
cf6f469e MF	5	#ifndef __CONFIG_BF537_STAMP_H__
cf6f469e MF	6	#define __CONFIG_BF537_STAMP_H__
26bf7dec	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
cf6f469e MF	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf537-0.2
cf6f469e	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
26bf7dec	15
cf6f469e MF	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 25000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
26bf7dec	31	#define CONFIG_VCO_MULT 20
cf6f469e MF	32	/* CCLK_DIV controls the core clock divider */
cf6f469e MF	33	/* Values can be 1, 2, 4, or 8 ONLY */
26bf7dec	34	#define CONFIG_CCLK_DIV 1
cf6f469e MF	35	/* SCLK_DIV controls the system clock divider */
cf6f469e MF	36	/* Values can range from 1-15 */
f82caacc	37	#define CONFIG_SCLK_DIV 4
26bf7dec	38
26bf7dec	39	/*
cf6f469e	40	* Memory Settings
26bf7dec	41	*/
cf6f469e MF	42	#define CONFIG_MEM_ADD_WDTH 10
	43	#define CONFIG_MEM_SIZE 64
	44
	45	#define CONFIG_EBIU_SDRRC_VAL 0x306
	46	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	47
	48	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	49	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	50	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	51
955020c6	52	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
cf6f469e MF	53	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
cf6f469e MF	54
26bf7dec AL	55	/*
	56	* Network Settings
	57	*/
cf6f469e MF	58	#ifndef __ADSPBF534__
	59	#define ADI_CMDS_NETWORK 1
	60	#define CONFIG_BFIN_MAC
	61	#define CONFIG_NETCONSOLE 1
26bf7dec	62	#endif
cf6f469e	63	#define CONFIG_HOSTNAME bf537-stamp
26bf7dec	64
079a136c	65	/*
cf6f469e	66	* Flash Settings
079a136c	67	*/
cf6f469e MF	68	#define CONFIG_FLASH_CFI_DRIVER
	69	#define CONFIG_SYS_FLASH_BASE 0x20000000
	70	#define CONFIG_SYS_FLASH_CFI
	71	#define CONFIG_SYS_FLASH_PROTECTION
	72	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	73	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
	74	#define CONFIG_SYS_MAX_FLASH_SECT 71
079a136c	75
ba2351f9	76	/*
cf6f469e	77	* SPI Settings
ba2351f9	78	*/
cf6f469e MF	79	#define CONFIG_BFIN_SPI
cf6f469e MF	80	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	81	#define CONFIG_SF_DEFAULT_SPEED 30000000
f453220c	82	#define CONFIG_SPI_FLASH_ALL
ba2351f9	83
cf6f469e MF	84	/*
	85	* Env Storage Settings
	86	*/
	87	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	88	#define CONFIG_ENV_IS_IN_SPI_FLASH
bc43a8d8	89	#define CONFIG_ENV_OFFSET 0x10000
cf6f469e	90	#define CONFIG_ENV_SIZE 0x2000
bc43a8d8	91	#define CONFIG_ENV_SECT_SIZE 0x10000
26bf7dec	92	#else
cf6f469e MF	93	#define CONFIG_ENV_IS_IN_FLASH
	94	#define CONFIG_ENV_OFFSET 0x4000
	95	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	96	#define CONFIG_ENV_SIZE 0x2000
	97	#define CONFIG_ENV_SECT_SIZE 0x2000
26bf7dec	98	#endif
cf6f469e MF	99	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
cf6f469e MF	100	#define ENV_IS_EMBEDDED
26bf7dec	101	#else
76d82187	102	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
26bf7dec	103	#endif
9ff67e5e MF	104	#ifdef ENV_IS_EMBEDDED
	105	/* WARNING - the following is hand-optimized to fit within
	106	* the sector before the environment sector. If it throws
	107	* an error during compilation remove an object here to get
	108	* it linked after the configuration sector.
	109	*/
	110	# define LDS_BOARD_TEXT \
e2906a59 MY	111	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	112	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	113	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	114	common/env_embedded.o (.text*);
9ff67e5e	115	#endif
6d0f6bcf	116
cf6f469e MF	117	/*
	118	* I2C Settings
	119	*/
c469703b	120	#define CONFIG_SYS_I2C
fea9b69a	121	#define CONFIG_SYS_I2C_ADI
26bf7dec	122
26bf7dec	123	/*
cf6f469e	124	* SPI_MMC Settings
26bf7dec	125	*/
955020c6 SZ	126	#define CONFIG_MMC_SPI
955020c6 SZ	127	#ifdef CONFIG_MMC_SPI
cf6f469e	128	#define CONFIG_MMC
14dda9df	129	#define CONFIG_GENERIC_MMC
955020c6	130	#endif
26bf7dec AL	131
26bf7dec AL	132	/*
cf6f469e	133	* NAND Settings
26bf7dec	134	*/
cd84423a	135	/* #define CONFIG_NAND_PLAT */
955020c6	136	#ifdef CONFIG_NAND_PLAT
cd84423a	137	#define CONFIG_SYS_NAND_BASE 0x20212000
6d0f6bcf	138	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd84423a MF	139
	140	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	141	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
cd84423a	142	#define BFIN_NAND_WRITE(addr, cmd) \
cf6f469e	143	do { \
cd84423a MF	144	bfin_write8(addr, cmd); \
cd84423a MF	145	SSYNC(); \
26bf7dec AL	146	} while (0)
26bf7dec AL	147
cd84423a MF	148	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
cd84423a MF	149	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
67ceefa7	150	#define NAND_PLAT_GPIO_DEV_READY GPIO_PF3
955020c6	151	#endif /* CONFIG_NAND_PLAT */
26bf7dec AL	152
26bf7dec AL	153	/*
cf6f469e	154	* CF-CARD IDE-HDD Support
26bf7dec	155	*/
aa7b248a MH	156
	157	/*
	158	* Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
	159	* Strange address mapping Blackfin A13 connects to CF_A0
	160	*/
	161
	162	/* #define CONFIG_BFIN_TRUE_IDE */
	163
	164	/*
	165	* Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
	166	* This should be the preferred mode
	167	*/
	168
	169	/* #define CONFIG_BFIN_CF_IDE */
	170
	171	/*
	172	* Add IDE Disk Drive (HDD) support
	173	* See example interface here:
	174	* http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
	175	*/
	176
	177	/* #define CONFIG_BFIN_HDD_IDE */
26bf7dec	178
cf6f469e MF	179	#if defined(CONFIG_BFIN_CF_IDE) \|\| \
	180	defined(CONFIG_BFIN_HDD_IDE) \|\| \
	181	defined(CONFIG_BFIN_TRUE_IDE)
	182	# define CONFIG_BFIN_IDE 1
	183	# define CONFIG_CMD_IDE
	184	#endif
26bf7dec	185
26bf7dec AL	186	#if defined(CONFIG_BFIN_IDE)
	187
	188	#define CONFIG_DOS_PARTITION 1
	189	/*
	190	* IDE/ATA stuff
	191	*/
	192	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	193	#undef CONFIG_IDE_LED /* no led for ide supported */
	194	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	195
cf6f469e MF	196	#define CONFIG_SYS_IDE_MAXBUS 1
cf6f469e MF	197	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
26bf7dec	198
cf6f469e MF	199	#undef CONFIG_EBIU_AMBCTL1_VAL
cf6f469e MF	200	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
26bf7dec AL	201
	202	#define CONFIG_CF_ATASEL_DIS 0x20311800
	203	#define CONFIG_CF_ATASEL_ENA 0x20311802
	204
	205	#if defined(CONFIG_BFIN_TRUE_IDE)
	206	/*
	207	* Note that these settings aren't for the most part used in include/ata.h
	208	* when all of the ATA registers are setup
	209	*/
6d0f6bcf JCPV	210	#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
6d0f6bcf JCPV	211	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	212	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	213	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	214	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
aa7b248a	215	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A13 */
26bf7dec	216
cf6f469e	217	#elif defined(CONFIG_BFIN_CF_IDE)
6d0f6bcf JCPV	218	#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
6d0f6bcf JCPV	219	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	220	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
	221	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
	222	#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
aa7b248a	223	#define CONFIG_SYS_ATA_STRIDE 1 /* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
26bf7dec	224
cf6f469e	225	#elif defined(CONFIG_BFIN_HDD_IDE)
6d0f6bcf JCPV	226	#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
6d0f6bcf JCPV	227	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	228	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	229	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	230	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
6d0f6bcf	231	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
26bf7dec AL	232	#undef CONFIG_SCLK_DIV
26bf7dec AL	233	#define CONFIG_SCLK_DIV 8
cf6f469e MF	234	#endif
	235
	236	#endif
26bf7dec	237
cf6f469e MF	238	/*
	239	* Misc Settings
	240	*/
	241	#define CONFIG_MISC_INIT_R
	242	#define CONFIG_RTC_BFIN
	243	#define CONFIG_UART_CONSOLE 0
	244
cf6f469e MF	245	/* Define if want to do post memory test */
	246	#undef CONFIG_POST
	247	#ifdef CONFIG_POST
0fc47444	248	#define CONFIG_SYS_POST_HOTKEYS_GPIO GPIO_PF5
2151374f MF	249	#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	250	GPIO_PF6, GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
	251	#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	252	GPIO_PF5, GPIO_PF4, GPIO_PF3, GPIO_PF2,
	253	#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	254	10, 11, 12, 13,
22f45ce4 MF	255	#define CONFIG_SYS_POST_FLASH_START 11
22f45ce4 MF	256	#define CONFIG_SYS_POST_FLASH_END 71
cf6f469e MF	257	#endif
cf6f469e MF	258
216818c1 MF	259	/* These are for board tests */
	260	#if 0
	261	#define CONFIG_BOOTCOMMAND "bootldr 0x203f0100"
216818c1 MF	262	#endif
216818c1 MF	263
cf6f469e MF	264	/*
	265	* Pull in common ADI header for remaining command/environment setup
	266	*/
	267	#include <configs/bfin_adi_common.h>
26bf7dec AL	268
26bf7dec AL	269	#endif