[people/ms/u-boot.git] / include / configs / bf537-stamp.h

/*
 * U-boot - Configuration file for BF537 STAMP board
 */

#ifndef __CONFIG_BF537_STAMP_H__
#define __CONFIG_BF537_STAMP_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			20
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	0x306
#define CONFIG_EBIU_SDGCTL_VAL	0x91114d

#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#define CONFIG_NET_MULTI	1
#endif
#define CONFIG_HOSTNAME		bf537-stamp
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
#define CONFIG_SYS_MAX_FLASH_SECT	71


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_ATMEL
#define CONFIG_SPI_FLASH_SPANSION
#define CONFIG_SPI_FLASH_STMICRO
#define CONFIG_SPI_FLASH_WINBOND


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define ENV_IS_EMBEDDED_CUSTOM
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	cpu/blackfin/traps.o		(.text .text.*); \
	cpu/blackfin/interrupt.o	(.text .text.*); \
	cpu/blackfin/serial.o		(.text .text.*); \
	common/dlmalloc.o		(.text .text.*); \
	lib_generic/crc32.o		(.text .text.*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o		(.text .text.*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_BFIN_TWI_I2C	1
#define CONFIG_HARD_I2C		1
#define CONFIG_SYS_I2C_SPEED	50000
#define CONFIG_SYS_I2C_SLAVE	0


/*
 * SPI_MMC Settings
 */
#define CONFIG_MMC
#define CONFIG_BFIN_SPI_MMC


/*
 * NAND Settings
 */
/* #define CONFIG_NAND_PLAT */
#define CONFIG_SYS_NAND_BASE		0x20212000
#define CONFIG_SYS_MAX_NAND_DEVICE	1

#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 2))
#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W | (1 << 1))
#define BFIN_NAND_READY     PF3
#define BFIN_NAND_WRITE(addr, cmd) \
	do { \
		bfin_write8(addr, cmd); \
		SSYNC(); \
	} while (0)

#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
#define NAND_PLAT_DEV_READY(chip)      (bfin_read_PORTFIO() & BFIN_NAND_READY)
#define NAND_PLAT_INIT() \
	do { \
		bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
		bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
		bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() | BFIN_NAND_READY); \
	} while (0)


/*
 * CF-CARD IDE-HDD Support
 */
/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */

#if defined(CONFIG_BFIN_CF_IDE) || \
    defined(CONFIG_BFIN_HDD_IDE) || \
    defined(CONFIG_BFIN_TRUE_IDE)
# define CONFIG_BFIN_IDE	1
# define CONFIG_CMD_IDE
#endif

#if defined(CONFIG_BFIN_IDE)

#define CONFIG_DOS_PARTITION	1
/*
 * IDE/ATA stuff
 */
#undef  CONFIG_IDE_8xx_DIRECT	/* no pcmcia interface required */
#undef  CONFIG_IDE_LED		/* no led for ide supported */
#undef  CONFIG_IDE_RESET	/* no reset for ide supported */

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS * 1)

#undef  CONFIG_EBIU_AMBCTL1_VAL
#define CONFIG_EBIU_AMBCTL1_VAL		0xFFC3FFC3

#define CONFIG_CF_ATASEL_DIS	0x20311800
#define CONFIG_CF_ATASEL_ENA	0x20311802

#if defined(CONFIG_BFIN_TRUE_IDE)
/*
 * Note that these settings aren't for the most part used in include/ata.h
 * when all of the ATA registers are setup
 */
#define CONFIG_SYS_ATA_BASE_ADDR	0x2031C000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */

#elif defined(CONFIG_BFIN_CF_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */

#elif defined(CONFIG_BFIN_HDD_IDE)
#define CONFIG_SYS_ATA_BASE_ADDR	0x20314000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A1 */
#undef  CONFIG_SCLK_DIV
#define CONFIG_SCLK_DIV		8
#endif

#endif


/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/* #define CONFIG_BF537_STAMP_LEDCMD	1 */

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define FLASH_START_POST_BLOCK	11	/* Should > = 11 */
#define FLASH_END_POST_BLOCK	71	/* Should < = 71 */
#endif


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
26bf7dec AL	1	/*
	2	* U-boot - Configuration file for BF537 STAMP board
	3	*/
	4
cf6f469e MF	5	#ifndef __CONFIG_BF537_STAMP_H__
cf6f469e MF	6	#define __CONFIG_BF537_STAMP_H__
26bf7dec	7
f348ab85	8	#include <asm/config-pre.h>
f7ce12cb	9
26bf7dec	10
cf6f469e MF	11	/*
	12	* Processor Settings
	13	*/
	14	#define CONFIG_BFIN_CPU bf537-0.2
	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
26bf7dec	16
26bf7dec	17
cf6f469e MF	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
26bf7dec	33	#define CONFIG_VCO_MULT 20
cf6f469e MF	34	/* CCLK_DIV controls the core clock divider */
cf6f469e MF	35	/* Values can be 1, 2, 4, or 8 ONLY */
26bf7dec	36	#define CONFIG_CCLK_DIV 1
cf6f469e MF	37	/* SCLK_DIV controls the system clock divider */
cf6f469e MF	38	/* Values can range from 1-15 */
f82caacc	39	#define CONFIG_SCLK_DIV 4
26bf7dec	40
26bf7dec AL	41
26bf7dec AL	42	/*
cf6f469e	43	* Memory Settings
26bf7dec	44	*/
cf6f469e MF	45	#define CONFIG_MEM_ADD_WDTH 10
	46	#define CONFIG_MEM_SIZE 64
	47
	48	#define CONFIG_EBIU_SDRRC_VAL 0x306
	49	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	52	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	53	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	54
6f5fd56f	55	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
cf6f469e MF	56	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
cf6f469e MF	57
26bf7dec AL	58
	59	/*
	60	* Network Settings
	61	*/
cf6f469e MF	62	#ifndef __ADSPBF534__
	63	#define ADI_CMDS_NETWORK 1
	64	#define CONFIG_BFIN_MAC
	65	#define CONFIG_NETCONSOLE 1
	66	#define CONFIG_NET_MULTI 1
26bf7dec	67	#endif
cf6f469e	68	#define CONFIG_HOSTNAME bf537-stamp
26bf7dec AL	69	/* Uncomment next line to use fixed MAC address */
26bf7dec AL	70	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
26bf7dec	71
26bf7dec	72
079a136c	73	/*
cf6f469e	74	* Flash Settings
079a136c	75	*/
cf6f469e MF	76	#define CONFIG_FLASH_CFI_DRIVER
	77	#define CONFIG_SYS_FLASH_BASE 0x20000000
	78	#define CONFIG_SYS_FLASH_CFI
	79	#define CONFIG_SYS_FLASH_PROTECTION
	80	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	81	/* some have 67 sectors (M29W320DB), but newer have 71 (M29W320EB) */
	82	#define CONFIG_SYS_MAX_FLASH_SECT 71
079a136c JL	83
079a136c JL	84
ba2351f9	85	/*
cf6f469e	86	* SPI Settings
ba2351f9	87	*/
cf6f469e MF	88	#define CONFIG_BFIN_SPI
cf6f469e MF	89	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	90	#define CONFIG_SF_DEFAULT_SPEED 30000000
cf6f469e MF	91	#define CONFIG_SPI_FLASH
	92	#define CONFIG_SPI_FLASH_ATMEL
	93	#define CONFIG_SPI_FLASH_SPANSION
	94	#define CONFIG_SPI_FLASH_STMICRO
	95	#define CONFIG_SPI_FLASH_WINBOND
ba2351f9	96
ba2351f9	97
cf6f469e MF	98	/*
	99	* Env Storage Settings
	100	*/
	101	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	102	#define CONFIG_ENV_IS_IN_SPI_FLASH
bc43a8d8	103	#define CONFIG_ENV_OFFSET 0x10000
cf6f469e	104	#define CONFIG_ENV_SIZE 0x2000
bc43a8d8	105	#define CONFIG_ENV_SECT_SIZE 0x10000
26bf7dec	106	#else
cf6f469e MF	107	#define CONFIG_ENV_IS_IN_FLASH
	108	#define CONFIG_ENV_OFFSET 0x4000
	109	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	110	#define CONFIG_ENV_SIZE 0x2000
	111	#define CONFIG_ENV_SECT_SIZE 0x2000
26bf7dec	112	#endif
cf6f469e MF	113	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
cf6f469e MF	114	#define ENV_IS_EMBEDDED
26bf7dec	115	#else
cf6f469e	116	#define ENV_IS_EMBEDDED_CUSTOM
26bf7dec	117	#endif
9ff67e5e MF	118	#ifdef ENV_IS_EMBEDDED
	119	/* WARNING - the following is hand-optimized to fit within
	120	* the sector before the environment sector. If it throws
	121	* an error during compilation remove an object here to get
	122	* it linked after the configuration sector.
	123	*/
	124	# define LDS_BOARD_TEXT \
	125	cpu/blackfin/traps.o (.text .text.*); \
	126	cpu/blackfin/interrupt.o (.text .text.*); \
	127	cpu/blackfin/serial.o (.text .text.*); \
	128	common/dlmalloc.o (.text .text.*); \
	129	lib_generic/crc32.o (.text .text.*); \
	130	. = DEFINED(env_offset) ? env_offset : .; \
	131	common/env_embedded.o (.text .text.*);
	132	#endif
6d0f6bcf	133
26bf7dec	134
cf6f469e MF	135	/*
	136	* I2C Settings
	137	*/
	138	#define CONFIG_BFIN_TWI_I2C 1
	139	#define CONFIG_HARD_I2C 1
	140	#define CONFIG_SYS_I2C_SPEED 50000
	141	#define CONFIG_SYS_I2C_SLAVE 0
26bf7dec	142
26bf7dec AL	143
26bf7dec AL	144	/*
cf6f469e	145	* SPI_MMC Settings
26bf7dec	146	*/
cf6f469e MF	147	#define CONFIG_MMC
cf6f469e MF	148	#define CONFIG_BFIN_SPI_MMC
26bf7dec	149
26bf7dec AL	150
26bf7dec AL	151	/*
cf6f469e	152	* NAND Settings
26bf7dec	153	*/
cd84423a MF	154	/* #define CONFIG_NAND_PLAT */
cd84423a MF	155	#define CONFIG_SYS_NAND_BASE 0x20212000
6d0f6bcf	156	#define CONFIG_SYS_MAX_NAND_DEVICE 1
cd84423a MF	157
	158	#define BFIN_NAND_CLE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 2))
	159	#define BFIN_NAND_ALE(chip) ((unsigned long)(chip)->IO_ADDR_W \| (1 << 1))
	160	#define BFIN_NAND_READY PF3
	161	#define BFIN_NAND_WRITE(addr, cmd) \
cf6f469e	162	do { \
cd84423a MF	163	bfin_write8(addr, cmd); \
cd84423a MF	164	SSYNC(); \
26bf7dec AL	165	} while (0)
26bf7dec AL	166
cd84423a MF	167	#define NAND_PLAT_WRITE_CMD(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_CLE(chip), cmd)
	168	#define NAND_PLAT_WRITE_ADR(chip, cmd) BFIN_NAND_WRITE(BFIN_NAND_ALE(chip), cmd)
	169	#define NAND_PLAT_DEV_READY(chip) (bfin_read_PORTFIO() & BFIN_NAND_READY)
	170	#define NAND_PLAT_INIT() \
	171	do { \
	172	bfin_write_PORTF_FER(bfin_read_PORTF_FER() & ~BFIN_NAND_READY); \
	173	bfin_write_PORTFIO_DIR(bfin_read_PORTFIO_DIR() & ~BFIN_NAND_READY); \
	174	bfin_write_PORTFIO_INEN(bfin_read_PORTFIO_INEN() \| BFIN_NAND_READY); \
	175	} while (0)
26bf7dec	176
26bf7dec AL	177
26bf7dec AL	178	/*
cf6f469e	179	* CF-CARD IDE-HDD Support
26bf7dec	180	*/
cf6f469e MF	181	/* #define CONFIG_BFIN_TRUE_IDE / / Add CF flash card support */
	182	/* #define CONFIG_BFIN_CF_IDE / / Add CF flash card support */
	183	/* #define CONFIG_BFIN_HDD_IDE / / Add IDE Disk Drive (HDD) support */
26bf7dec	184
cf6f469e MF	185	#if defined(CONFIG_BFIN_CF_IDE) \|\| \
	186	defined(CONFIG_BFIN_HDD_IDE) \|\| \
	187	defined(CONFIG_BFIN_TRUE_IDE)
	188	# define CONFIG_BFIN_IDE 1
	189	# define CONFIG_CMD_IDE
	190	#endif
26bf7dec	191
26bf7dec AL	192	#if defined(CONFIG_BFIN_IDE)
	193
	194	#define CONFIG_DOS_PARTITION 1
	195	/*
	196	* IDE/ATA stuff
	197	*/
	198	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	199	#undef CONFIG_IDE_LED /* no led for ide supported */
	200	#undef CONFIG_IDE_RESET /* no reset for ide supported */
	201
cf6f469e MF	202	#define CONFIG_SYS_IDE_MAXBUS 1
cf6f469e MF	203	#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
26bf7dec	204
cf6f469e MF	205	#undef CONFIG_EBIU_AMBCTL1_VAL
cf6f469e MF	206	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC3FFC3
26bf7dec AL	207
	208	#define CONFIG_CF_ATASEL_DIS 0x20311800
	209	#define CONFIG_CF_ATASEL_ENA 0x20311802
	210
	211	#if defined(CONFIG_BFIN_TRUE_IDE)
	212	/*
	213	* Note that these settings aren't for the most part used in include/ata.h
	214	* when all of the ATA registers are setup
	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_ATA_BASE_ADDR 0x2031C000
6d0f6bcf JCPV	217	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	218	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	219	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	220	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
6d0f6bcf	221	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.Ax */
26bf7dec	222
cf6f469e	223	#elif defined(CONFIG_BFIN_CF_IDE)
6d0f6bcf JCPV	224	#define CONFIG_SYS_ATA_BASE_ADDR 0x20211800
6d0f6bcf JCPV	225	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	226	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* data I/O */
	227	#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* normal register accesses */
	228	#define CONFIG_SYS_ATA_ALT_OFFSET 0x000E /* alternate registers */
6d0f6bcf	229	#define CONFIG_SYS_ATA_STRIDE 1 /* CF.A0 --> Blackfin.Ax */
26bf7dec	230
cf6f469e	231	#elif defined(CONFIG_BFIN_HDD_IDE)
6d0f6bcf JCPV	232	#define CONFIG_SYS_ATA_BASE_ADDR 0x20314000
6d0f6bcf JCPV	233	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
cf6f469e MF	234	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
	235	#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
	236	#define CONFIG_SYS_ATA_ALT_OFFSET 0x001C /* alternate registers */
6d0f6bcf	237	#define CONFIG_SYS_ATA_STRIDE 2 /* CF.A0 --> Blackfin.A1 */
26bf7dec AL	238	#undef CONFIG_SCLK_DIV
26bf7dec AL	239	#define CONFIG_SCLK_DIV 8
cf6f469e MF	240	#endif
	241
	242	#endif
26bf7dec	243
cf6f469e MF	244
	245	/*
	246	* Misc Settings
	247	*/
	248	#define CONFIG_MISC_INIT_R
	249	#define CONFIG_RTC_BFIN
	250	#define CONFIG_UART_CONSOLE 0
	251
	252	/* #define CONFIG_BF537_STAMP_LEDCMD 1 */
	253
	254	/* Define if want to do post memory test */
	255	#undef CONFIG_POST
	256	#ifdef CONFIG_POST
	257	#define FLASH_START_POST_BLOCK 11 /* Should > = 11 */
	258	#define FLASH_END_POST_BLOCK 71 /* Should < = 71 */
	259	#endif
	260
	261
	262	/*
	263	* Pull in common ADI header for remaining command/environment setup
	264	*/
	265	#include <configs/bfin_adi_common.h>
26bf7dec AL	266
26bf7dec AL	267	#endif