[people/ms/u-boot.git] / include / configs / bf538f-ezkit.h

/*
 * U-Boot - Configuration file for BF538F EZ-Kit Lite board
 */

#ifndef __CONFIG_BF538F_EZKIT_H__
#define __CONFIG_BF538F_EZKIT_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf538-0.4
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_SDRRC_VAL	(0x03F6)
#define CONFIG_EBIU_SDGCTL_VAL	(SCTLE | PSS | TWR_2 | TRCD_3 | TRP_3 | TRAS_6 | PASR_ALL | CL_3)

#define CONFIG_EBIU_AMGCTL_VAL	(CDPRIO | AMBEN_ALL | AMCKEN)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(384 * 1024)

/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC91111	1
#define CONFIG_SMC91111_BASE	0x20310300
#define CONFIG_HOSTNAME		bf538f-ezkit

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	71

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
/*
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH_ALL
*/

/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x2000
#else
#define	CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		0x2000
#define	CONFIG_ENV_SECT_SIZE	0x2000
#endif
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * Misc Settings
 */
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
5c45f7ca	1	/*
a187559e	2	* U-Boot - Configuration file for BF538F EZ-Kit Lite board
5c45f7ca MF	3	*/
	4
	5	#ifndef __CONFIG_BF538F_EZKIT_H__
	6	#define __CONFIG_BF538F_EZKIT_H__
	7
f348ab85	8	#include <asm/config-pre.h>
5c45f7ca	9
5c45f7ca MF	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf538-0.4
5c45f7ca MF	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
5c45f7ca MF	15
5c45f7ca MF	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 25000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 21
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 4
	38
5c45f7ca MF	39	/*
	40	* Memory Settings
	41	*/
	42	#define CONFIG_MEM_ADD_WDTH 10
	43	#define CONFIG_MEM_SIZE 64
	44
	45	#define CONFIG_EBIU_SDRRC_VAL (0x03F6)
	46	#define CONFIG_EBIU_SDGCTL_VAL (SCTLE \| PSS \| TWR_2 \| TRCD_3 \| TRP_3 \| TRAS_6 \| PASR_ALL \| CL_3)
	47
	48	#define CONFIG_EBIU_AMGCTL_VAL (CDPRIO \| AMBEN_ALL \| AMCKEN)
	49	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	50	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	51
	52	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	53	#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
	54
5c45f7ca MF	55	/*
	56	* Network Settings
	57	*/
	58	#define ADI_CMDS_NETWORK 1
7194ab80	59	#define CONFIG_SMC91111 1
5c45f7ca MF	60	#define CONFIG_SMC91111_BASE 0x20310300
5c45f7ca MF	61	#define CONFIG_HOSTNAME bf538f-ezkit
5c45f7ca	62
5c45f7ca MF	63	/*
	64	* Flash Settings
	65	*/
	66	#define CONFIG_FLASH_CFI_DRIVER
	67	#define CONFIG_SYS_FLASH_BASE 0x20000000
	68	#define CONFIG_SYS_FLASH_CFI
	69	#define CONFIG_SYS_FLASH_PROTECTION
	70	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	71	#define CONFIG_SYS_MAX_FLASH_SECT 71
	72
5c45f7ca MF	73	/*
	74	* SPI Settings
	75	*/
	76	#define CONFIG_BFIN_SPI
	77	#define CONFIG_ENV_SPI_MAX_HZ 30000000
c49eabef	78	/*
afac8b07	79	#define CONFIG_SF_DEFAULT_SPEED 30000000
f453220c	80	#define CONFIG_SPI_FLASH_ALL
c49eabef	81	*/
5c45f7ca MF	82
	83	/*
	84	* Env Storage Settings
	85	*/
	86	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	87	#define CONFIG_ENV_IS_IN_SPI_FLASH
	88	#define CONFIG_ENV_OFFSET 0x4000
	89	#define CONFIG_ENV_SIZE 0x2000
	90	#define CONFIG_ENV_SECT_SIZE 0x2000
	91	#else
	92	#define CONFIG_ENV_IS_IN_FLASH
	93	#define CONFIG_ENV_OFFSET 0x4000
	94	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	95	#define CONFIG_ENV_SIZE 0x2000
	96	#define CONFIG_ENV_SECT_SIZE 0x2000
	97	#endif
	98	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	99	#define ENV_IS_EMBEDDED
	100	#else
76d82187	101	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
5c45f7ca	102	#endif
9ff67e5e MF	103	#ifdef ENV_IS_EMBEDDED
	104	/* WARNING - the following is hand-optimized to fit within
	105	* the sector before the environment sector. If it throws
	106	* an error during compilation remove an object here to get
	107	* it linked after the configuration sector.
	108	*/
	109	# define LDS_BOARD_TEXT \
e2906a59 MY	110	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	111	arch/blackfin/cpu/built-in.o (.text*); \
9ff67e5e	112	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	113	common/env_embedded.o (.text*);
9ff67e5e	114	#endif
5c45f7ca	115
5c45f7ca MF	116	/*
	117	* I2C Settings
	118	*/
c469703b	119	#define CONFIG_SYS_I2C
fea9b69a	120	#define CONFIG_SYS_I2C_ADI
5c45f7ca	121
5c45f7ca MF	122	/*
	123	* Misc Settings
	124	*/
	125	#define CONFIG_RTC_BFIN
	126	#define CONFIG_UART_CONSOLE 0
5c45f7ca MF	127
	128	/*
	129	* Pull in common ADI header for remaining command/environment setup
	130	*/
	131	#include <configs/bfin_adi_common.h>
	132
5c45f7ca	133	#endif