[people/ms/u-boot.git] / include / configs / bf548-ezkit.h

/*
 * U-Boot - Configuration file for BF548 STAMP board
 */

#ifndef __CONFIG_BF548_EZKIT_H__
#define __CONFIG_BF548_EZKIT_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf548-0.0
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021

/* Default EZ-Kit bank mapping:
 *	Async Bank 0 - 32MB Burst Flash
 *	Async Bank 1 - Ethernet
 *	Async Bank 2 - Nothing
 *	Async Bank 3 - Nothing
 */
#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)

#define CONFIG_SYS_MONITOR_LEN	(1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(768 * 1024)

/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC911X	1
#define CONFIG_SMC911X_BASE	0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME		bf548-ezkit

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	259

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000

/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET	0x60000
#define CONFIG_ENV_SIZE		0x20000
#else
/* The BF548-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET	(0x1000000 - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE	0x8000
#endif

/*
 * NAND Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_BFIN_NFC_CTL_VAL        0x0033
#define CONFIG_BFIN_NFC_BOOTROM_ECC
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE           0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE     1
#endif

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * SATA
 */
#if !defined(__ADSPBF544__)
#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#define CONFIG_PATA_BFIN
#define CONFIG_BFIN_ATAPI_BASE_ADDR	0xFFC03800
#define CONFIG_BFIN_ATA_MODE	XFER_PIO_4
#endif

/*
 * SDH Settings
 */
#if !defined(__ADSPBF544__)
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif

/*
 * USB Settings
 */
#if !defined(__ADSPBF544__)
#define CONFIG_USB_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_MUSB_TIMEOUT 100000
#endif

/*
 * Misc Settings
 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000

#define CONFIG_ADI_GPIO2

#ifdef CONFIG_VIDEO
#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
#define CONFIG_DEB_DMA_URGENT
#endif

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	13, 12, 11, 10,
#define CONFIG_SYS_POST_FLASH_START	10
#define CONFIG_SYS_POST_FLASH_END	127
#endif

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
76d21803	1	/*
a187559e	2	* U-Boot - Configuration file for BF548 STAMP board
76d21803 MF	3	*/
	4
	5	#ifndef __CONFIG_BF548_EZKIT_H__
	6	#define __CONFIG_BF548_EZKIT_H__
	7
f348ab85	8	#include <asm/config-pre.h>
76d21803	9
76d21803 MF	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf548-0.0
76d21803 MF	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
76d21803 MF	15
76d21803 MF	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 25000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 21
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 4
	38
76d21803 MF	39	/*
	40	* Memory Settings
	41	*/
	42	#define CONFIG_MEM_ADD_WDTH 10
	43	#define CONFIG_MEM_SIZE 64
	44
	45	#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
	46	#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
	47	#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
	48
	49	/* Default EZ-Kit bank mapping:
	50	* Async Bank 0 - 32MB Burst Flash
	51	* Async Bank 1 - Ethernet
	52	* Async Bank 2 - Nothing
	53	* Async Bank 3 - Nothing
	54	*/
	55	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	56	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	57	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	58	#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
	59	#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
	60
fea63e2a	61	#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
76d21803 MF	62	#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
76d21803 MF	63
76d21803 MF	64	/*
	65	* Network Settings
	66	*/
	67	#define ADI_CMDS_NETWORK 1
736fead8 BW	68	#define CONFIG_SMC911X 1
	69	#define CONFIG_SMC911X_BASE 0x24000000
	70	#define CONFIG_SMC911X_16_BIT
76d21803	71	#define CONFIG_HOSTNAME bf548-ezkit
76d21803	72
76d21803 MF	73	/*
	74	* Flash Settings
	75	*/
	76	#define CONFIG_FLASH_CFI_DRIVER
	77	#define CONFIG_SYS_FLASH_BASE 0x20000000
	78	#define CONFIG_SYS_FLASH_CFI
	79	#define CONFIG_SYS_FLASH_PROTECTION
	80	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	81	#define CONFIG_SYS_MAX_FLASH_SECT 259
	82
76d21803 MF	83	/*
	84	* SPI Settings
	85	*/
	86	#define CONFIG_BFIN_SPI
	87	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	88	#define CONFIG_SF_DEFAULT_SPEED 30000000
76d21803	89
76d21803 MF	90	/*
	91	* Env Storage Settings
	92	*/
	93	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	94	#define CONFIG_ENV_IS_IN_SPI_FLASH
	95	#define CONFIG_ENV_OFFSET 0x10000
	96	#define CONFIG_ENV_SIZE 0x2000
	97	#define CONFIG_ENV_SECT_SIZE 0x10000
76d82187	98	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
76d21803 MF	99	#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
76d21803 MF	100	#define CONFIG_ENV_IS_IN_NAND
d413dbc9	101	#define CONFIG_ENV_OFFSET 0x60000
76d21803 MF	102	#define CONFIG_ENV_SIZE 0x20000
76d21803 MF	103	#else
1b48f126	104	/* The BF548-EZKIT uses a top boot flash */
76d21803	105	#define CONFIG_ENV_IS_IN_FLASH 1
1b48f126 MF	106	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	107	#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
	108	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	109	#define CONFIG_ENV_SECT_SIZE 0x8000
76d21803 MF	110	#endif
76d21803 MF	111
76d21803 MF	112	/*
	113	* NAND Settings
	114	*/
76d21803	115	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
e0ae433e BL	116	#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
e0ae433e BL	117	#define CONFIG_BFIN_NFC_BOOTROM_ECC
76d21803	118	#define CONFIG_DRIVER_NAND_BFIN
e0ae433e BL	119	#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
	120	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	121	#endif
76d21803 MF	122
	123	/*
	124	* I2C Settings
	125	*/
c469703b	126	#define CONFIG_SYS_I2C
fea9b69a	127	#define CONFIG_SYS_I2C_ADI
76d21803	128
76d21803 MF	129	/*
	130	* SATA
	131	*/
	132	#if !defined(__ADSPBF544__)
	133	#define CONFIG_LIBATA
	134	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	135	#define CONFIG_LBA48
	136	#define CONFIG_PATA_BFIN
	137	#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
	138	#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
	139	#endif
	140
76d21803 MF	141	/*
	142	* SDH Settings
	143	*/
	144	#if !defined(__ADSPBF544__)
e54c8209	145	#define CONFIG_GENERIC_MMC
76d21803 MF	146	#define CONFIG_MMC
	147	#define CONFIG_BFIN_SDH
	148	#endif
	149
76d21803 MF	150	/*
	151	* USB Settings
	152	*/
	153	#if !defined(__ADSPBF544__)
95de1e2f	154	#define CONFIG_USB_MUSB_HCD
76d21803	155	#define CONFIG_USB_BLACKFIN
95de1e2f	156	#define CONFIG_USB_MUSB_TIMEOUT 100000
76d21803 MF	157	#endif
76d21803 MF	158
76d21803 MF	159	/*
	160	* Misc Settings
	161	*/
	162	#define CONFIG_BOARD_EARLY_INIT_F
58d7570c	163	#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
76d21803 MF	164	#define CONFIG_RTC_BFIN
76d21803 MF	165	#define CONFIG_UART_CONSOLE 1
abaa5ba4	166	#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
76d21803	167
da34aae5 SZ	168	#define CONFIG_ADI_GPIO2
da34aae5 SZ	169
e0ae433e BL	170	#ifdef CONFIG_VIDEO
	171	#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
	172	#define CONFIG_DEB_DMA_URGENT
76d21803 MF	173	#endif
	174
	175	/* Define if want to do post memory test */
	176	#undef CONFIG_POST
	177	#ifdef CONFIG_POST
2151374f MF	178	#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	179	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
	180	#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	181	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
	182	#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	183	13, 12, 11, 10,
22f45ce4 MF	184	#define CONFIG_SYS_POST_FLASH_START 10
22f45ce4 MF	185	#define CONFIG_SYS_POST_FLASH_END 127
76d21803 MF	186	#endif
76d21803 MF	187
76d21803 MF	188	/*
	189	* Pull in common ADI header for remaining command/environment setup
	190	*/
	191	#include <configs/bfin_adi_common.h>
	192
76d21803	193	#endif