[people/ms/u-boot.git] / include / configs / bf548-ezkit.h

/*
 * U-boot - Configuration file for BF548 STAMP board
 */

#ifndef __CONFIG_BF548_EZKIT_H__
#define __CONFIG_BF548_EZKIT_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf548-0.0
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	10
#define CONFIG_MEM_SIZE		64

#define CONFIG_EBIU_DDRCTL0_VAL	0x218A83FE
#define CONFIG_EBIU_DDRCTL1_VAL	0x20022222
#define CONFIG_EBIU_DDRCTL2_VAL	0x00000021

/* Default EZ-Kit bank mapping:
 *	Async Bank 0 - 32MB Burst Flash
 *	Async Bank 1 - Ethernet
 *	Async Bank 2 - Nothing
 *	Async Bank 3 - Nothing
 */
#define CONFIG_EBIU_AMGCTL_VAL	0xFF
#define CONFIG_EBIU_AMBCTL0_VAL	0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL	0xFFC27BB0
#define CONFIG_EBIU_FCTL_VAL	(BCLK_4)
#define CONFIG_EBIU_MODE_VAL	(B0MODE_FLASH)

#define CONFIG_SYS_MONITOR_LEN	(1024 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(768 * 1024)


/*
 * Network Settings
 */
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC911X	1
#define CONFIG_SMC911X_BASE	0x24000000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_HOSTNAME		bf548-ezkit
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	259


/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000
#define CONFIG_SF_DEFAULT_SPEED	30000000
#define CONFIG_SPI_FLASH
#define CONFIG_SPI_FLASH_STMICRO


/*
 * Env Storage Settings
 */
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x10000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x10000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET	0x60000
#define CONFIG_ENV_SIZE		0x20000
#else
/* The BF548-EZKIT uses a top boot flash */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET	(0x1000000 - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE	0x8000
#endif


/*
 * NAND Settings
 */
#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
# define CONFIG_BFIN_NFC_BOOTROM_ECC
#endif
#define CONFIG_DRIVER_NAND_BFIN
#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE	1


/*
 * I2C Settings
 */
#define CONFIG_BFIN_TWI_I2C	1
#define CONFIG_HARD_I2C		1


/*
 * SATA
 */
#if !defined(__ADSPBF544__)
#define CONFIG_LIBATA
#define CONFIG_SYS_SATA_MAX_DEVICE 1
#define CONFIG_LBA48
#define CONFIG_PATA_BFIN
#define CONFIG_BFIN_ATAPI_BASE_ADDR	0xFFC03800
#define CONFIG_BFIN_ATA_MODE	XFER_PIO_4
#endif


/*
 * SDH Settings
 */
#if !defined(__ADSPBF544__)
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_BFIN_SDH
#endif


/*
 * USB Settings
 */
#if !defined(__ADSPBF544__)
#define CONFIG_USB
#define CONFIG_MUSB_HCD
#define CONFIG_USB_BLACKFIN
#define CONFIG_USB_STORAGE
#define CONFIG_MUSB_TIMEOUT 100000
#endif


/*
 * Misc Settings
 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	1
#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000

#ifndef __ADSPBF542__
/* Don't waste time transferring a logo over the UART */
# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
#  define CONFIG_VIDEO
# endif
# define CONFIG_DEB_DMA_URGENT
#endif

/* Define if want to do post memory test */
#undef CONFIG_POST
#ifdef CONFIG_POST
#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	13, 12, 11, 10,
#define CONFIG_SYS_POST_FLASH_START	10
#define CONFIG_SYS_POST_FLASH_END	127
#endif


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
76d21803 MF	1	/*
	2	* U-boot - Configuration file for BF548 STAMP board
	3	*/
	4
	5	#ifndef __CONFIG_BF548_EZKIT_H__
	6	#define __CONFIG_BF548_EZKIT_H__
	7
f348ab85	8	#include <asm/config-pre.h>
76d21803 MF	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf548-0.0
76d21803 MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 21
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 4
	40
	41
	42	/*
	43	* Memory Settings
	44	*/
	45	#define CONFIG_MEM_ADD_WDTH 10
	46	#define CONFIG_MEM_SIZE 64
	47
	48	#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
	49	#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
	50	#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
	51
	52	/* Default EZ-Kit bank mapping:
	53	* Async Bank 0 - 32MB Burst Flash
	54	* Async Bank 1 - Ethernet
	55	* Async Bank 2 - Nothing
	56	* Async Bank 3 - Nothing
	57	*/
	58	#define CONFIG_EBIU_AMGCTL_VAL 0xFF
	59	#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
	60	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
	61	#define CONFIG_EBIU_FCTL_VAL (BCLK_4)
	62	#define CONFIG_EBIU_MODE_VAL (B0MODE_FLASH)
	63
fea63e2a	64	#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
76d21803 MF	65	#define CONFIG_SYS_MALLOC_LEN (768 * 1024)
	66
	67
	68	/*
	69	* Network Settings
	70	*/
	71	#define ADI_CMDS_NETWORK 1
736fead8 BW	72	#define CONFIG_SMC911X 1
	73	#define CONFIG_SMC911X_BASE 0x24000000
	74	#define CONFIG_SMC911X_16_BIT
76d21803 MF	75	#define CONFIG_HOSTNAME bf548-ezkit
	76	/* Uncomment next line to use fixed MAC address */
	77	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
	78
	79
	80	/*
	81	* Flash Settings
	82	*/
	83	#define CONFIG_FLASH_CFI_DRIVER
	84	#define CONFIG_SYS_FLASH_BASE 0x20000000
	85	#define CONFIG_SYS_FLASH_CFI
	86	#define CONFIG_SYS_FLASH_PROTECTION
	87	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	88	#define CONFIG_SYS_MAX_FLASH_SECT 259
	89
	90
	91	/*
	92	* SPI Settings
	93	*/
	94	#define CONFIG_BFIN_SPI
	95	#define CONFIG_ENV_SPI_MAX_HZ 30000000
afac8b07	96	#define CONFIG_SF_DEFAULT_SPEED 30000000
76d21803 MF	97	#define CONFIG_SPI_FLASH
	98	#define CONFIG_SPI_FLASH_STMICRO
	99
	100
	101	/*
	102	* Env Storage Settings
	103	*/
	104	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
	105	#define CONFIG_ENV_IS_IN_SPI_FLASH
	106	#define CONFIG_ENV_OFFSET 0x10000
	107	#define CONFIG_ENV_SIZE 0x2000
	108	#define CONFIG_ENV_SECT_SIZE 0x10000
76d82187	109	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
76d21803 MF	110	#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
76d21803 MF	111	#define CONFIG_ENV_IS_IN_NAND
d413dbc9	112	#define CONFIG_ENV_OFFSET 0x60000
76d21803 MF	113	#define CONFIG_ENV_SIZE 0x20000
76d21803 MF	114	#else
1b48f126	115	/* The BF548-EZKIT uses a top boot flash */
76d21803	116	#define CONFIG_ENV_IS_IN_FLASH 1
1b48f126 MF	117	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	118	#define CONFIG_ENV_OFFSET (0x1000000 - CONFIG_ENV_SECT_SIZE)
	119	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	120	#define CONFIG_ENV_SECT_SIZE 0x8000
76d21803 MF	121	#endif
	122
	123
	124	/*
	125	* NAND Settings
	126	*/
	127	#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
	128	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
	129	# define CONFIG_BFIN_NFC_BOOTROM_ECC
	130	#endif
	131	#define CONFIG_DRIVER_NAND_BFIN
	132	#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
	133	#define CONFIG_SYS_MAX_NAND_DEVICE 1
76d21803 MF	134
	135
	136	/*
	137	* I2C Settings
	138	*/
	139	#define CONFIG_BFIN_TWI_I2C 1
	140	#define CONFIG_HARD_I2C 1
76d21803 MF	141
	142
	143	/*
	144	* SATA
	145	*/
	146	#if !defined(__ADSPBF544__)
	147	#define CONFIG_LIBATA
	148	#define CONFIG_SYS_SATA_MAX_DEVICE 1
	149	#define CONFIG_LBA48
	150	#define CONFIG_PATA_BFIN
	151	#define CONFIG_BFIN_ATAPI_BASE_ADDR 0xFFC03800
	152	#define CONFIG_BFIN_ATA_MODE XFER_PIO_4
	153	#endif
	154
	155
	156	/*
	157	* SDH Settings
	158	*/
	159	#if !defined(__ADSPBF544__)
e54c8209	160	#define CONFIG_GENERIC_MMC
76d21803 MF	161	#define CONFIG_MMC
	162	#define CONFIG_BFIN_SDH
	163	#endif
	164
	165
	166	/*
	167	* USB Settings
	168	*/
	169	#if !defined(__ADSPBF544__)
	170	#define CONFIG_USB
	171	#define CONFIG_MUSB_HCD
	172	#define CONFIG_USB_BLACKFIN
	173	#define CONFIG_USB_STORAGE
	174	#define CONFIG_MUSB_TIMEOUT 100000
	175	#endif
	176
	177
	178	/*
	179	* Misc Settings
	180	*/
	181	#define CONFIG_BOARD_EARLY_INIT_F
58d7570c	182	#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
76d21803 MF	183	#define CONFIG_RTC_BFIN
76d21803 MF	184	#define CONFIG_UART_CONSOLE 1
abaa5ba4	185	#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
76d21803 MF	186
	187	#ifndef __ADSPBF542__
	188	/* Don't waste time transferring a logo over the UART */
	189	# if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART)
	190	# define CONFIG_VIDEO
	191	# endif
	192	# define CONFIG_DEB_DMA_URGENT
	193	#endif
	194
	195	/* Define if want to do post memory test */
	196	#undef CONFIG_POST
	197	#ifdef CONFIG_POST
2151374f MF	198	#define CONFIG_POST_BSPEC1_GPIO_LEDS \
	199	GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
	200	#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
	201	GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
	202	#define CONFIG_POST_BSPEC2_GPIO_NAMES \
	203	13, 12, 11, 10,
22f45ce4 MF	204	#define CONFIG_SYS_POST_FLASH_START 10
22f45ce4 MF	205	#define CONFIG_SYS_POST_FLASH_END 127
76d21803 MF	206	#endif
	207
	208
	209	/*
	210	* Pull in common ADI header for remaining command/environment setup
	211	*/
	212	#include <configs/bfin_adi_common.h>
	213
76d21803	214	#endif