[people/ms/u-boot.git] / include / configs / blackvme.h

/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
 * The board includes ADSP-BF561 rev. 0.5,
 * 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
 * Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
 * SPI  boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
 * FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
 * Spartan6-LX150 (memory-mapped; both PPIs also connected).
 * See http://www.skutek.com
 */

#ifndef __CONFIG_BLACKVME_H__
#define __CONFIG_BLACKVME_H__

#include <asm/config-pre.h>

/* Debugging: Set these options if you're having problems
 * #define CONFIG_DEBUG_EARLY_SERIAL
 * #define DEBUG
 * #define CONFIG_DEBUG_DUMP
 * #define CONFIG_DEBUG_DUMP_SYMS
 * CONFIG_PANIC_HANG means that the board will not auto-reboot
 */
#define CONFIG_PANIC_HANG 0

/* CPU Options */
#define CONFIG_BFIN_CPU        bf561-0.5
#define CONFIG_BFIN_BOOT_MODE  BFIN_BOOT_SPI_MASTER

/*
 *		CLOCK SETTINGS CAVEAT
 * You CANNOT just change the clock settings, esp. the SCLK.
 * The SDRAM timing, SPI baud, and the serial UART baud
 * use SCLK frequency to set their own frequencies. Therefore,
 * if you change the SCLK_DIV, you may also have to adjust
 * SDRAM refresh and other timings.
 * --------------------------------------------------------------
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *		25 *  8 / 1 = 200 MHz
 *		25 * 16 / 1 = 400 MHz
 *		25 * 24 / 1 = 600 MHz
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 *		25 *  8 / 2 = 100 MHz
 *		25 * 24 / 6 = 100 MHz
 *		25 * 24 / 5 = 120 MHz
 *		25 * 16 / 3 = 133 MHz
 * 25 MHz because the oscillator also feeds the ether chip.
 * CONFIG_CLKIN_HZ is 25 MHz written in Hz
 * CLKIN_HALF controls the DF bit in PLL_CTL
 *	0 = CLKIN	1 = CLKIN / 2
 * PLL_BYPASS controls the BYPASS bit in PLL_CTL
 *	0 = do not bypass	1 = bypass PLL
 * VCO_MULT = MSEL (multiplier) in PLL_CTL
 * Values can range from 0-63 (where 0 means 64)
 * CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
 * SCLK_DIV = system clock divider, 1 to 15
 */
#define CONFIG_CLKIN_HZ		25000000
#define CONFIG_CLKIN_HALF	0
#define CONFIG_PLL_BYPASS	0
#define CONFIG_VCO_MULT		8
#define CONFIG_CCLK_DIV		1
#define CONFIG_SCLK_DIV		2

/*
 * Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
 * Used in 32-bit mode. 16-bit mode not supported.
 * http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
 */
/*
 * Network settings using a dedicated 2nd ether card in PC
 * Windows will automatically acquire IP of that card
 * Then use the dedicated card IP + 1 for the board
 * http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
 */
#define CONFIG_DRIVER_AX88180	1
#define AX88180_BASE		0x2c000000
#define CONFIG_CMD_MII		/* enable probing PHY */

#define CONFIG_HOSTNAME	blackvme	/* Bfin board  */
#define CONFIG_IPADDR		169.254.144.145	/* Bfin board  */
#define CONFIG_GATEWAYIP	169.254.144.144	/* dedic card  */
#define CONFIG_SERVERIP	169.254.144.144	/* tftp server */
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_ROOTPATH		"/export/uClinux-dist/romfs"	/*NFS*/
#define CFG_AUTOLOAD		"no"
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_PING

/*
 * SDRAM settings & memory map
 */

#define CONFIG_MEM_SIZE		64	/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH	 9	/* 8, 9, 10, 11    */
/*
 * SDRAM reference page
 * http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
 * NOTE: BlackVME populates only SDRAM bank 0
 */
/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
#define CONFIG_EBIU_SDGCTL_VAL  0x91114d  /* global control */
#define CONFIG_EBIU_SDRRC_VAL   0x306     /* refresh rate */

/* Async memory global settings. (ASRAM, not SDRAM)
 * HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
 * CLKOUT enabled, all async banks enabled, core has priority
 * bank 0&1 16 bit (FPGA)
 * bank 2&3 32 bit (ether and USB chips)
 */
#define CONFIG_EBIU_AMGCTL_VAL  0x3F   /* ASRAM setup */

/* Async mem timing: BF561 HRM page 16-12 and 16-15.
 * Default values 0xFFC2 FFC2 are the slowest supported.
 * Example settings of CONFIG_EBIU_AMBCTL1_VAL
 * 1. EZ-KIT settings: 0xFFC2 7BB0
 * 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
 *    See the following page:
 *    http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
 * 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
 * AX88180  WEN = 5 clocks  REN 6 clocks @ SCLK = 100 MHz
 * One extra clock needed because AX88180 is asynchronous to CPU.
 */
			   /* bank 1   0 */
#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
			   /* bank 3   2 */
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2

/* memory layout */

#define CONFIG_SYS_MONITOR_LEN	(256 << 10)
#define CONFIG_SYS_MALLOC_LEN	(384 << 10)

/*
 * Serial SPI Flash
 * For the M25P64 SCK should be kept < 15 MHz
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_OFFSET	0x40000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x40000

#define CONFIG_ENV_SPI_MAX_HZ	15000000
#define CONFIG_SF_DEFAULT_SPEED	15000000

/*
 * Interactive command settings
 */

#define CONFIG_SYS_LONGHELP	1
#define CONFIG_CMDLINE_EDITING	1
#define CONFIG_AUTO_COMPLETE	1

#define CONFIG_CMD_BOOTLDR
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_CPLBINFO
#define CONFIG_CMD_SF

/*
 * Default: boot from SPI flash.
 * "sfboot" is a composite command defined in extra settings
 */
#define CONFIG_BOOTDELAY	5
#define CONFIG_BOOTCOMMAND	"run sfboot"

/*
 * Console settings
 */
#define CONFIG_BAUDRATE		57600
#define CONFIG_LOADS_ECHO	1
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BFIN_SERIAL

/*
 * U-Boot environment variables. Use "printenv" to examine.
 * http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
 */
#define CONFIG_BOOTARGS \
	"root=/dev/mtdblock0 rw " \
	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
	"earlyprintk=serial,uart0," \
	__stringify(CONFIG_BAUDRATE) " " \
	"console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "

/* Convenience env variables & commands.
 * Reserve kernstart = 0x20000  = 128 kB for U-Boot.
 * Reserve kernarea  = 0x500000 = 5 MB   for kernel (reasonable size).
 * U-Boot image is saved at flash offset=0.
 * Kernel image is saved at flash offset=$kernstart.
 * Instructions. Ksave takes about a minute to complete.
 *	1. Update U-Boot: run uget; run usave
 *	2. Update kernel: run kget; run ksave
 * After updating U-Boot also update the kernel per above instructions
 * to make the saved environment consistent with the flash.
 */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"kernstart=0x20000\0" \
	"kernarea=0x500000\0" \
	"uget=tftp u-boot.ldr\0" \
	"kget=tftp uImage\0" \
	"usave=sf probe 2; " \
		"sf erase 0 $(kernstart); " \
		"sf write $(fileaddr) 0 $(filesize)\0" \
	"ksave=sf probe 2; " \
		"saveenv; " \
		"echo Now patiently wait for the prompt...; " \
		"sf erase $(kernstart) $(kernarea); " \
		"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
	"sfboot=sf probe 2; " \
		"sf read $(loadaddr) $(kernstart) $(filesize); " \
		"run addip; bootm\0" \
	"addip=setenv bootargs $(bootargs) " \
	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
		"$(netmask):$(hostname):eth0:off\0"

/*
 * Soft I2C settings (BF561 does not have hard I2C)
 * PF12,13 on SPI connector 0.
 */
#ifdef CONFIG_SYS_I2C_SOFT
# define CONFIG_CMD_I2C
# define CONFIG_SOFT_I2C_GPIO_SCL	GPIO_PF12
# define CONFIG_SOFT_I2C_GPIO_SDA	GPIO_PF13
# define CONFIG_SYS_I2C_SPEED		50000
# define CONFIG_SYS_I2C_SLAVE		0xFE
#endif

/*
 * No Parallel Flash on this board
 */
#define CONFIG_SYS_NO_FLASH
#undef CONFIG_CMD_JFFS2

#endif
Commit	Line	Data
3bbed7f8 WS	1	/* U-boot for BlackVME. (C) Wojtek Skulski 2010.
	2	* The board includes ADSP-BF561 rev. 0.5,
	3	* 32-bit SDRAM (2 * MT48LC16M16A2TG or MT48LC32M16A2TG),
	4	* Gigabit Ether AX88180 (ASIX) + 88E1111 rev. B2 (Marvell),
	5	* SPI boot flash on PF2 (M25P64 8MB, or M25P128 16 MB),
	6	* FPGA boot flash on PF3 (M25P64 8MB, or M25P128 16 MB),
	7	* Spartan6-LX150 (memory-mapped; both PPIs also connected).
	8	* See http://www.skutek.com
	9	*/
	10
	11	#ifndef __CONFIG_BLACKVME_H__
	12	#define __CONFIG_BLACKVME_H__
	13
	14	#include <asm/config-pre.h>
	15
	16	/* Debugging: Set these options if you're having problems
	17	* #define CONFIG_DEBUG_EARLY_SERIAL
	18	* #define DEBUG
	19	* #define CONFIG_DEBUG_DUMP
	20	* #define CONFIG_DEBUG_DUMP_SYMS
	21	* CONFIG_PANIC_HANG means that the board will not auto-reboot
	22	*/
	23	#define CONFIG_PANIC_HANG 0
	24
	25	/* CPU Options */
fbcf8e8c MF	26	#define CONFIG_BFIN_CPU bf561-0.5
fbcf8e8c MF	27	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_SPI_MASTER
3bbed7f8 WS	28
	29	/*
	30	* CLOCK SETTINGS CAVEAT
	31	* You CANNOT just change the clock settings, esp. the SCLK.
	32	* The SDRAM timing, SPI baud, and the serial UART baud
	33	* use SCLK frequency to set their own frequencies. Therefore,
	34	* if you change the SCLK_DIV, you may also have to adjust
	35	* SDRAM refresh and other timings.
	36	* --------------------------------------------------------------
	37	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	38	* 25 * 8 / 1 = 200 MHz
	39	* 25 * 16 / 1 = 400 MHz
	40	* 25 * 24 / 1 = 600 MHz
	41	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	42	* 25 * 8 / 2 = 100 MHz
	43	* 25 * 24 / 6 = 100 MHz
	44	* 25 * 24 / 5 = 120 MHz
	45	* 25 * 16 / 3 = 133 MHz
	46	* 25 MHz because the oscillator also feeds the ether chip.
	47	* CONFIG_CLKIN_HZ is 25 MHz written in Hz
	48	* CLKIN_HALF controls the DF bit in PLL_CTL
	49	* 0 = CLKIN 1 = CLKIN / 2
	50	* PLL_BYPASS controls the BYPASS bit in PLL_CTL
	51	* 0 = do not bypass 1 = bypass PLL
	52	* VCO_MULT = MSEL (multiplier) in PLL_CTL
	53	* Values can range from 0-63 (where 0 means 64)
	54	* CCLK_DIV = core clock divider (1, 2, 4, or 8 ONLY)
	55	* SCLK_DIV = system clock divider, 1 to 15
	56	*/
	57	#define CONFIG_CLKIN_HZ 25000000
	58	#define CONFIG_CLKIN_HALF 0
	59	#define CONFIG_PLL_BYPASS 0
	60	#define CONFIG_VCO_MULT 8
	61	#define CONFIG_CCLK_DIV 1
	62	#define CONFIG_SCLK_DIV 2
	63
	64	/*
	65	* Ether chip in async memory space AMS3, same as BF561-EZ-KIT.
	66	* Used in 32-bit mode. 16-bit mode not supported.
	67	* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
	68	*/
	69	/*
	70	* Network settings using a dedicated 2nd ether card in PC
	71	* Windows will automatically acquire IP of that card
	72	* Then use the dedicated card IP + 1 for the board
	73	* http://docs.blackfin.uclinux.org/doku.php?id=setting_up_the_network
	74	*/
3bbed7f8 WS	75	#define CONFIG_DRIVER_AX88180 1
	76	#define AX88180_BASE 0x2c000000
	77	#define CONFIG_CMD_MII /* enable probing PHY */
	78
31a4f1e5 MF	79	#define CONFIG_HOSTNAME blackvme /* Bfin board */
	80	#define CONFIG_IPADDR 169.254.144.145 /* Bfin board */
	81	#define CONFIG_GATEWAYIP 169.254.144.144 /* dedic card */
	82	#define CONFIG_SERVERIP 169.254.144.144 /* tftp server */
	83	#define CONFIG_NETMASK 255.255.255.0
8b3637c6	84	#define CONFIG_ROOTPATH "/export/uClinux-dist/romfs" /NFS/
31a4f1e5 MF	85	#define CFG_AUTOLOAD "no"
	86	#define CONFIG_CMD_DHCP
	87	#define CONFIG_CMD_PING
3bbed7f8 WS	88
	89	/*
	90	* SDRAM settings & memory map
	91	*/
	92
	93	#define CONFIG_MEM_SIZE 64 /* 128, 64, 32, 16 */
	94	#define CONFIG_MEM_ADD_WDTH 9 /* 8, 9, 10, 11 */
	95	/*
	96	* SDRAM reference page
	97	* http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
	98	* NOTE: BlackVME populates only SDRAM bank 0
	99	*/
	100	/* CONFIG_EBIU_SDBCTL_VAL bank ctrl may be needed in future */
	101	#define CONFIG_EBIU_SDGCTL_VAL 0x91114d /* global control */
	102	#define CONFIG_EBIU_SDRRC_VAL 0x306 /* refresh rate */
	103
	104	/* Async memory global settings. (ASRAM, not SDRAM)
	105	* HRM page 16-10. Global ASRAM control = 0x3F. Six lower bits = 1
	106	* CLKOUT enabled, all async banks enabled, core has priority
	107	* bank 0&1 16 bit (FPGA)
	108	* bank 2&3 32 bit (ether and USB chips)
	109	*/
	110	#define CONFIG_EBIU_AMGCTL_VAL 0x3F /* ASRAM setup */
	111
	112	/* Async mem timing: BF561 HRM page 16-12 and 16-15.
	113	* Default values 0xFFC2 FFC2 are the slowest supported.
	114	* Example settings of CONFIG_EBIU_AMBCTL1_VAL
	115	* 1. EZ-KIT settings: 0xFFC2 7BB0
	116	* 2. Bank 3 good timing for AX88180 @ 125MHz = 0x8850 xxxx
	117	* See the following page:
	118	* http://docs.blackfin.uclinux.org/doku.php?id=hw:cards:ax88180
	119	* 3. Bank 3 timing for AX88180 @ SCLK = 100 MHz:
	120	* AX88180 WEN = 5 clocks REN 6 clocks @ SCLK = 100 MHz
	121	* One extra clock needed because AX88180 is asynchronous to CPU.
	122	*/
071bc923	123	/* bank 1 0 */
3bbed7f8	124	#define CONFIG_EBIU_AMBCTL0_VAL 0xFFC2FFC2
071bc923	125	/* bank 3 2 */
3bbed7f8 WS	126	#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC2FFC2
	127
	128	/* memory layout */
	129
	130	#define CONFIG_SYS_MONITOR_LEN (256 << 10)
	131	#define CONFIG_SYS_MALLOC_LEN (384 << 10)
	132
	133	/*
	134	* Serial SPI Flash
	135	* For the M25P64 SCK should be kept < 15 MHz
	136	*/
	137	#define CONFIG_BFIN_SPI
	138	#define CONFIG_ENV_IS_IN_SPI_FLASH
	139	#define CONFIG_ENV_OFFSET 0x40000
	140	#define CONFIG_ENV_SIZE 0x2000
	141	#define CONFIG_ENV_SECT_SIZE 0x40000
	142
	143	#define CONFIG_ENV_SPI_MAX_HZ 15000000
	144	#define CONFIG_SF_DEFAULT_SPEED 15000000
3bbed7f8 WS	145
	146	/*
	147	* Interactive command settings
	148	*/
	149
	150	#define CONFIG_SYS_LONGHELP 1
	151	#define CONFIG_CMDLINE_EDITING 1
	152	#define CONFIG_AUTO_COMPLETE 1
	153
3bbed7f8 WS	154	#define CONFIG_CMD_BOOTLDR
	155	#define CONFIG_CMD_CACHE
	156	#define CONFIG_CMD_CPLBINFO
	157	#define CONFIG_CMD_SF
3bbed7f8 WS	158
	159	/*
	160	* Default: boot from SPI flash.
	161	* "sfboot" is a composite command defined in extra settings
	162	*/
	163	#define CONFIG_BOOTDELAY 5
	164	#define CONFIG_BOOTCOMMAND "run sfboot"
	165
	166	/*
	167	* Console settings
	168	*/
	169	#define CONFIG_BAUDRATE 57600
	170	#define CONFIG_LOADS_ECHO 1
	171	#define CONFIG_UART_CONSOLE 0
7b27a685	172	#define CONFIG_BFIN_SERIAL
3bbed7f8 WS	173
	174	/*
	175	* U-Boot environment variables. Use "printenv" to examine.
	176	* http://docs.blackfin.uclinux.org/doku.php?id=bootloaders:u-boot:env
	177	*/
	178	#define CONFIG_BOOTARGS \
	179	"root=/dev/mtdblock0 rw " \
5368c55d	180	"clkin_hz=" __stringify(CONFIG_CLKIN_HZ) " " \
3bbed7f8	181	"earlyprintk=serial,uart0," \
5368c55d MV	182	__stringify(CONFIG_BAUDRATE) " " \
5368c55d MV	183	"console=ttyBF0," __stringify(CONFIG_BAUDRATE) " "
3bbed7f8 WS	184
	185	/* Convenience env variables & commands.
	186	* Reserve kernstart = 0x20000 = 128 kB for U-Boot.
	187	* Reserve kernarea = 0x500000 = 5 MB for kernel (reasonable size).
	188	* U-Boot image is saved at flash offset=0.
	189	* Kernel image is saved at flash offset=$kernstart.
	190	* Instructions. Ksave takes about a minute to complete.
	191	* 1. Update U-Boot: run uget; run usave
	192	* 2. Update kernel: run kget; run ksave
	193	* After updating U-Boot also update the kernel per above instructions
	194	* to make the saved environment consistent with the flash.
	195	*/
	196	#define CONFIG_EXTRA_ENV_SETTINGS \
	197	"kernstart=0x20000\0" \
	198	"kernarea=0x500000\0" \
	199	"uget=tftp u-boot.ldr\0" \
	200	"kget=tftp uImage\0" \
	201	"usave=sf probe 2; " \
	202	"sf erase 0 $(kernstart); " \
	203	"sf write $(fileaddr) 0 $(filesize)\0" \
	204	"ksave=sf probe 2; " \
	205	"saveenv; " \
	206	"echo Now patiently wait for the prompt...; " \
	207	"sf erase $(kernstart) $(kernarea); " \
	208	"sf write $(fileaddr) $(kernstart) $(filesize)\0" \
	209	"sfboot=sf probe 2; " \
	210	"sf read $(loadaddr) $(kernstart) $(filesize); " \
	211	"run addip; bootm\0" \
	212	"addip=setenv bootargs $(bootargs) " \
	213	"ip=$(ipaddr):$(serverip):$(gatewayip):" \
	214	"$(netmask):$(hostname):eth0:off\0"
	215
	216	/*
	217	* Soft I2C settings (BF561 does not have hard I2C)
	218	* PF12,13 on SPI connector 0.
	219	*/
ea818dbb	220	#ifdef CONFIG_SYS_I2C_SOFT
3bbed7f8 WS	221	# define CONFIG_CMD_I2C
	222	# define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF12
	223	# define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF13
	224	# define CONFIG_SYS_I2C_SPEED 50000
	225	# define CONFIG_SYS_I2C_SLAVE 0xFE
	226	#endif
	227
	228	/*
	229	* No Parallel Flash on this board
	230	*/
	231	#define CONFIG_SYS_NO_FLASH
3bbed7f8	232	#undef CONFIG_CMD_JFFS2
3bbed7f8 WS	233
3bbed7f8 WS	234	#endif