[people/ms/u-boot.git] / include / configs / calimain.h

/*
 * Copyright (C) 2011-2014 OMICRON electronics GmbH
 *
 * Based on da850evm.h. Original Copyrights follow:
 *
 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * Board
 */
#define CONFIG_DRIVER_TI_EMAC
#define CONFIG_MACH_TYPE	MACH_TYPE_CALIMAIN

/*
 * SoC Configuration
 */
#define CONFIG_MACH_DAVINCI_CALIMAIN
#define CONFIG_SOC_DA8XX		/* TI DA8xx SoC */
#define CONFIG_SOC_DA850		/* TI DA850 SoC */
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
#define CONFIG_SYS_CLK_FREQ		clk_get(DAVINCI_ARM_CLKID)
#define CONFIG_SYS_OSCIN_FREQ		calimain_get_osc_freq()
#define CONFIG_SYS_TIMERBASE		DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK		clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_SYS_TEXT_BASE		0x60000000
#define CONFIG_DA850_LOWLEVEL
#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DA8XX_GPIO
#define CONFIG_HW_WATCHDOG
#define CONFIG_SYS_WDTTIMERBASE	DAVINCI_TIMER1_BASE
#define CONFIG_SYS_WDT_PERIOD_LOW \
	(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
#define CONFIG_SYS_WDT_PERIOD_HIGH	0x0
#define CONFIG_SYS_DV_NOR_BOOT_CFG	(0x11)

/*
 * PLL configuration
 */
#define CONFIG_SYS_DV_CLKMODE          0
#define CONFIG_SYS_DA850_PLL0_POSTDIV  1
#define CONFIG_SYS_DA850_PLL0_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL0_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL0_PLLDIV3  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV4  0x8003
#define CONFIG_SYS_DA850_PLL0_PLLDIV5  0x8002
#define CONFIG_SYS_DA850_PLL0_PLLDIV6  CONFIG_SYS_DA850_PLL0_PLLDIV1
#define CONFIG_SYS_DA850_PLL0_PLLDIV7  0x8005

#define CONFIG_SYS_DA850_PLL1_POSTDIV  1
#define CONFIG_SYS_DA850_PLL1_PLLDIV1  0x8000
#define CONFIG_SYS_DA850_PLL1_PLLDIV2  0x8001
#define CONFIG_SYS_DA850_PLL1_PLLDIV3  0x8002

#define CONFIG_SYS_DA850_PLL0_PLLM \
	((calimain_get_osc_freq() == 25000000) ? 23 : 24)
#define CONFIG_SYS_DA850_PLL1_PLLM \
	((calimain_get_osc_freq() == 25000000) ? 20 : 21)

/*
 * DDR2 memory configuration
 */
#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
					DV_DDR_PHY_EXT_STRBEN | \
					(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDBCR (		\
	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) |	\
	(1 << DV_DDR_SDCR_DDREN_SHIFT) |	\
	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) |	\
	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) |	\
	(0x3 << DV_DDR_SDCR_CL_SHIFT) |		\
	(0x3 << DV_DDR_SDCR_IBANK_SHIFT) |	\
	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))

/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
#define CONFIG_SYS_DA850_DDR2_SDBCR2	0

#define CONFIG_SYS_DA850_DDR2_SDTIMR (		\
	(16 << DV_DDR_SDTMR1_RFC_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_RP_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RCD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WR_SHIFT) |		\
	(5 << DV_DDR_SDTMR1_RAS_SHIFT) |	\
	(7 << DV_DDR_SDTMR1_RC_SHIFT) |		\
	(1 << DV_DDR_SDTMR1_RRD_SHIFT) |	\
	(1 << DV_DDR_SDTMR1_WTR_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDTIMR2 (		\
	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) |	\
	(2 << DV_DDR_SDTMR2_XP_SHIFT) |		\
	(0 << DV_DDR_SDTMR2_ODT_SHIFT) |	\
	(18 << DV_DDR_SDTMR2_XSNR_SHIFT) |	\
	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) |	\
	(0 << DV_DDR_SDTMR2_RTP_SHIFT) |	\
	(2 << DV_DDR_SDTMR2_CKE_SHIFT))

#define CONFIG_SYS_DA850_DDR2_SDRCR	0x000003FF
#define CONFIG_SYS_DA850_DDR2_PBBPR	0x30

/*
 * Flash memory timing
 */

#define CONFIG_SYS_DA850_CS2CFG	(	\
	DAVINCI_ABCR_WSETUP(2) |	\
	DAVINCI_ABCR_WSTROBE(5)	|	\
	DAVINCI_ABCR_WHOLD(3) |		\
	DAVINCI_ABCR_RSETUP(1) |	\
	DAVINCI_ABCR_RSTROBE(14) |	\
	DAVINCI_ABCR_RHOLD(0) |		\
	DAVINCI_ABCR_TA(3) |		\
	DAVINCI_ABCR_ASIZE_16BIT)

/* single 64 MB NOR flash device connected to CS2 and CS3 */
#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG

/*
 * Memory Info
 */
#define CONFIG_SYS_MALLOC_LEN	(0x10000 + 1*1024*1024) /* malloc() len */
#define PHYS_SDRAM_1		DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
#define PHYS_SDRAM_1_SIZE	(128 << 20) /* SDRAM size 128MB */
#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/

#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC (	\
	DAVINCI_SYSCFG_SUSPSRC_TIMER0 |		\
	DAVINCI_SYSCFG_SUSPSRC_SPI1 |		\
	DAVINCI_SYSCFG_SUSPSRC_UART2 |		\
	DAVINCI_SYSCFG_SUSPSRC_EMAC |		\
	DAVINCI_SYSCFG_SUSPSRC_I2C)

/* memtest start addr */
#define CONFIG_SYS_MEMTEST_START	(PHYS_SDRAM_1 + 0x2000000)

/* memtest will be run on 16MB */
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (16 << 20))

#define CONFIG_NR_DRAM_BANKS	1 /* we have 1 bank of DRAM */

/*
 * Serial Driver info
 */
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	-4	/* NS16550 register size */
#define CONFIG_SYS_NS16550_COM1	DAVINCI_UART2_BASE /* Base address of UART2 */
#define CONFIG_SYS_NS16550_CLK	clk_get(DAVINCI_UART2_CLKID)
#define CONFIG_CONS_INDEX	1		/* use UART0 for console */

#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#define CONFIG_SYS_MAX_FLASH_BANKS  1 /* max number of flash banks */
#define CONFIG_SYS_FLASH_SECT_SZ    (128 << 10) /* 128KB */
#define CONFIG_SYS_FLASH_BASE       DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
#define CONFIG_ENV_SECT_SIZE        CONFIG_SYS_FLASH_SECT_SZ
#define CONFIG_ENV_ADDR \
	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
#define CONFIG_ENV_SIZE             (128 << 10)
#define CONFIG_ENV_ADDR_REDUND      (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND      CONFIG_ENV_SIZE
#define PHYS_FLASH_SIZE             (64 << 20) /* Flash size 64MB */
#define CONFIG_SYS_MAX_FLASH_SECT \
	((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)

/*
 * Network & Ethernet Configuration
 */
#ifdef CONFIG_DRIVER_TI_EMAC
#define CONFIG_EMAC_MDIO_PHY_NUM	1
#define CONFIG_MII
#define CONFIG_BOOTP_DNS
#define CONFIG_BOOTP_DNS2
#define CONFIG_BOOTP_SEND_HOSTNAME
#define CONFIG_NET_RETRY_COUNT	10
#endif

/*
 * U-Boot general configuration
 */
#define CONFIG_BOOTFILE        "uImage" /* Boot file name */
#define CONFIG_SYS_CBSIZE      1024 /* Console I/O Buffer Size	*/
#define CONFIG_SYS_PBSIZE      (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS     16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE    CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
#define CONFIG_SYS_LOAD_ADDR   (PHYS_SDRAM_1 + 0x700000)
#define CONFIG_LOADADDR        0xc0700000
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SYS_LONGHELP
#define CONFIG_CRC32_VERIFY
#define CONFIG_MX_CYCLIC

/*
 * Linux Information
 */
#define LINUX_BOOT_PARAM_ADDR     (PHYS_SDRAM_1 + 0x100)
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_BOOTARGS           ""
#define CONFIG_BOOTCOMMAND        "run checkupdate; run checkbutton;"
#define CONFIG_BOOT_RETRY_TIME    60  /* continue boot after 60 s inactivity */
#define CONFIG_RESET_TO_RETRY

/*
 * Default environment settings
 * gpio0 = button, gpio1 = led green, gpio2 = led red
 * verify = n ... disable kernel checksum verification for faster booting
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"tftpdir=calimero\0"						\
	"flashkernel=tftpboot $loadaddr $tftpdir/uImage; "		\
		"erase 0x60800000 +0x400000; "				\
		"cp.b $loadaddr 0x60800000 $filesize\0"			\
	"flashrootfs="							\
		"tftpboot $loadaddr $tftpdir/rootfs.jffs2; "		\
		"erase 0x60c00000 +0x2e00000; "				\
		"cp.b $loadaddr 0x60c00000 $filesize\0"			\
	"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; "		\
		"protect off all; "					\
		"erase 0x60000000 +0x80000; "				\
		"cp.b $loadaddr 0x60000000 $filesize\0"			\
	"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; "		\
		"erase 0x60080000 +0x780000; "				\
		"cp.b $loadaddr 0x60080000 $filesize\0"			\
	"erase_persistent=erase 0x63a00000 +0x600000;\0"		\
	"bootnor=setenv bootargs console=ttyS2,115200n8 "		\
		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
		"rootwait ethaddr=$ethaddr; "				\
		"gpio c 1; gpio s 2; bootm 0x60800000\0"		\
	"bootrlk=gpio s 1; gpio s 2;"					\
		"setenv bootargs console=ttyS2,115200n8 "		\
		"ethaddr=$ethaddr; bootm 0x60080000\0"			\
	"boottftp=setenv bootargs console=ttyS2,115200n8 "		\
		"root=/dev/mtdblock3 rw rootfstype=jffs2 "		\
		"rootwait ethaddr=$ethaddr; "				\
		"tftpboot $loadaddr $tftpdir/uImage;"			\
		"gpio c 1; gpio s 2; bootm $loadaddr\0"			\
	"checkupdate=if test -n $update_flag; then "			\
		"echo Previous update failed - starting RLK; "		\
		"run bootrlk; fi; "					\
		"if test -n $initial_setup; then "			\
		"echo Running initial setup procedure; "		\
		"sleep 1; run flashall; fi\0"				\
	"product=accessory\0"						\
	"serial=XX12345\0"						\
	"checknor="							\
		"if gpio i 0; then run bootnor; fi;\0"			\
	"checkrlk="							\
		"if gpio i 0; then run bootrlk; fi;\0"			\
	"checkbutton="							\
		"run checknor; sleep 1;"				\
		"run checknor; sleep 1;"				\
		"run checknor; sleep 1;"				\
		"run checknor; sleep 1;"				\
		"run checknor;"						\
		"gpio s 1; gpio s 2;"					\
		"echo ---- Release button to boot RLK ----;"		\
		"run checkrlk; sleep 1;"				\
		"run checkrlk; sleep 1;"				\
		"run checkrlk; sleep 1;"				\
		"run checkrlk; sleep 1;"				\
		"run checkrlk; sleep 1;"				\
		"run checkrlk;"						\
		"echo ---- Factory reset requested ----;"		\
		"gpio c 1;"						\
		"setenv factory_reset true;"				\
		"saveenv;"						\
		"run bootnor;\0"					\
	"flashall=run flashrlk;"					\
		"run flashkernel;"					\
		"run flashrootfs;"					\
		"setenv erase_datafs true;"				\
		"setenv initial_setup;"					\
		"saveenv;"						\
		"run bootnor;\0"					\
	"verify=n\0"							\
	"clearenv=protect off all;"					\
		"erase 0x60040000 +0x40000;\0"				\
	"bootlimit=3\0"							\
	"altbootcmd=run bootrlk\0"

#define CONFIG_PREBOOT			\
	"echo Version: $ver; "		\
	"echo Serial: $serial; "	\
	"echo MAC: $ethaddr; "		\
	"echo Product: $product; "	\
	"gpio c 1; gpio c 2;"

/*
 * U-Boot commands
 */
#define CONFIG_CMD_ENV
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_SAVES

#ifndef CONFIG_DRIVER_TI_EMAC
#endif

/* additions for new relocation code, must added to all boards */
#define CONFIG_SYS_SDRAM_BASE		0xc0000000
/* initial stack pointer in internal SRAM */
#define CONFIG_SYS_INIT_SP_ADDR		(0x8001ff00)

#define CONFIG_BOOTCOUNT_LIMIT
#define CONFIG_SYS_BOOTCOUNT_LE		/* Use little-endian accessors */
#define CONFIG_SYS_BOOTCOUNT_ADDR	DAVINCI_RTC_BASE

#ifndef __ASSEMBLY__
int calimain_get_osc_freq(void);
#endif

#endif /* __CONFIG_H */
Commit	Line	Data
9a3aae22	1	/*
30493aac	2	* Copyright (C) 2011-2014 OMICRON electronics GmbH
9a3aae22 CR	3	*
	4	* Based on da850evm.h. Original Copyrights follow:
	5	*
	6	* Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
	7	* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
	8	*
1a459660	9	* SPDX-License-Identifier: GPL-2.0+
9a3aae22 CR	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* Board
	17	*/
	18	#define CONFIG_DRIVER_TI_EMAC
9a3aae22 CR	19	#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
	20
	21	/*
	22	* SoC Configuration
	23	*/
	24	#define CONFIG_MACH_DAVINCI_CALIMAIN
9a3aae22 CR	25	#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
	26	#define CONFIG_SOC_DA850 /* TI DA850 SoC */
	27	#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
	28	#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
	29	#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
	30	#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
	31	#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
9a3aae22 CR	32	#define CONFIG_SYS_TEXT_BASE 0x60000000
9a3aae22 CR	33	#define CONFIG_DA850_LOWLEVEL
9a3aae22 CR	34	#define CONFIG_ARCH_CPU_INIT
	35	#define CONFIG_DA8XX_GPIO
	36	#define CONFIG_HW_WATCHDOG
	37	#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
	38	#define CONFIG_SYS_WDT_PERIOD_LOW \
	39	(60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
	40	#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
	41	#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
	42
	43	/*
	44	* PLL configuration
	45	*/
	46	#define CONFIG_SYS_DV_CLKMODE 0
	47	#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
	48	#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
	49	#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
	50	#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
	51	#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
	52	#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
	53	#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
	54	#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
	55
	56	#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
	57	#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
	58	#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
	59	#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
	60
	61	#define CONFIG_SYS_DA850_PLL0_PLLM \
	62	((calimain_get_osc_freq() == 25000000) ? 23 : 24)
	63	#define CONFIG_SYS_DA850_PLL1_PLLM \
	64	((calimain_get_osc_freq() == 25000000) ? 20 : 21)
	65
	66	/*
	67	* DDR2 memory configuration
	68	*/
	69	#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN \| \
	70	DV_DDR_PHY_EXT_STRBEN \| \
	71	(0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
	72
	73	#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
	74	(1 << DV_DDR_SDCR_DDR2EN_SHIFT) \| \
	75	(1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) \| \
	76	(1 << DV_DDR_SDCR_DDREN_SHIFT) \| \
	77	(1 << DV_DDR_SDCR_SDRAMEN_SHIFT) \| \
	78	(1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) \| \
	79	(0x3 << DV_DDR_SDCR_CL_SHIFT) \| \
	80	(0x3 << DV_DDR_SDCR_IBANK_SHIFT) \| \
	81	(0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
	82
	83	/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
	84	#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
	85
	86	#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
	87	(16 << DV_DDR_SDTMR1_RFC_SHIFT) \| \
	88	(1 << DV_DDR_SDTMR1_RP_SHIFT) \| \
	89	(1 << DV_DDR_SDTMR1_RCD_SHIFT) \| \
	90	(1 << DV_DDR_SDTMR1_WR_SHIFT) \| \
	91	(5 << DV_DDR_SDTMR1_RAS_SHIFT) \| \
	92	(7 << DV_DDR_SDTMR1_RC_SHIFT) \| \
	93	(1 << DV_DDR_SDTMR1_RRD_SHIFT) \| \
	94	(1 << DV_DDR_SDTMR1_WTR_SHIFT))
	95
	96	#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
	97	(7 << DV_DDR_SDTMR2_RASMAX_SHIFT) \| \
98	(2 << DV_DDR_SDTMR2_XP_SHIFT) \| \
99	(0 << DV_DDR_SDTMR2_ODT_SHIFT) \| \
100	(18 << DV_DDR_SDTMR2_XSNR_SHIFT) \| \
101	(199 << DV_DDR_SDTMR2_XSRD_SHIFT) \| \
102	(0 << DV_DDR_SDTMR2_RTP_SHIFT) \| \
103	(2 << DV_DDR_SDTMR2_CKE_SHIFT))
104
105	#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
106	#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
107
108	/*
109	* Flash memory timing
110	*/
111
112	#define CONFIG_SYS_DA850_CS2CFG ( \
113	DAVINCI_ABCR_WSETUP(2) \| \
114	DAVINCI_ABCR_WSTROBE(5) \| \
115	DAVINCI_ABCR_WHOLD(3) \| \
116	DAVINCI_ABCR_RSETUP(1) \| \
117	DAVINCI_ABCR_RSTROBE(14) \| \
118	DAVINCI_ABCR_RHOLD(0) \| \
119	DAVINCI_ABCR_TA(3) \| \
120	DAVINCI_ABCR_ASIZE_16BIT)
121
122	/* single 64 MB NOR flash device connected to CS2 and CS3 */
123	#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
124
125	/*
126	* Memory Info
127	*/
128	#define CONFIG_SYS_MALLOC_LEN (0x10000 + 110241024) /* malloc() len */
129	#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
130	#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
131	#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
132
133	#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
134	DAVINCI_SYSCFG_SUSPSRC_TIMER0 \| \
135	DAVINCI_SYSCFG_SUSPSRC_SPI1 \| \
136	DAVINCI_SYSCFG_SUSPSRC_UART2 \| \
137	DAVINCI_SYSCFG_SUSPSRC_EMAC \| \
138	DAVINCI_SYSCFG_SUSPSRC_I2C)
139
140	/* memtest start addr */
141	#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
142
143	/* memtest will be run on 16MB */
144	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
145
146	#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
9a3aae22 CR	147
	148	/*
	149	* Serial Driver info
	150	*/
9a3aae22 CR	151	#define CONFIG_SYS_NS16550_SERIAL
	152	#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
	153	#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
	154	#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
	155	#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
9a3aae22 CR	156
	157	#define CONFIG_ENV_IS_IN_FLASH
	158	#define CONFIG_FLASH_CFI_DRIVER
	159	#define CONFIG_SYS_FLASH_CFI
	160	#define CONFIG_SYS_FLASH_PROTECTION
	161	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	162	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
	163	#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
	164	#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
	165	#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
	166	#define CONFIG_ENV_ADDR \
	167	(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
	168	#define CONFIG_ENV_SIZE (128 << 10)
	169	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	170	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	171	#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
	172	#define CONFIG_SYS_MAX_FLASH_SECT \
	173	((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
	174
	175	/*
	176	* Network & Ethernet Configuration
	177	*/
	178	#ifdef CONFIG_DRIVER_TI_EMAC
	179	#define CONFIG_EMAC_MDIO_PHY_NUM 1
	180	#define CONFIG_MII
9a3aae22 CR	181	#define CONFIG_BOOTP_DNS
	182	#define CONFIG_BOOTP_DNS2
	183	#define CONFIG_BOOTP_SEND_HOSTNAME
	184	#define CONFIG_NET_RETRY_COUNT 10
	185	#endif
	186
	187	/*
	188	* U-Boot general configuration
	189	*/
	190	#define CONFIG_BOOTFILE "uImage" /* Boot file name */
9a3aae22 CR	191	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	192	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
	193	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	194	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
	195	#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
	196	#define CONFIG_LOADADDR 0xc0700000
9a3aae22	197	#define CONFIG_AUTO_COMPLETE
9a3aae22 CR	198	#define CONFIG_CMDLINE_EDITING
	199	#define CONFIG_SYS_LONGHELP
	200	#define CONFIG_CRC32_VERIFY
	201	#define CONFIG_MX_CYCLIC
	202
	203	/*
	204	* Linux Information
	205	*/
	206	#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
	207	#define CONFIG_CMDLINE_TAG
	208	#define CONFIG_REVISION_TAG
	209	#define CONFIG_SETUP_MEMORY_TAGS
	210	#define CONFIG_BOOTARGS ""
	211	#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
9a3aae22	212	#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
9a3aae22 CR	213	#define CONFIG_RESET_TO_RETRY
	214
	215	/*
	216	* Default environment settings
	217	* gpio0 = button, gpio1 = led green, gpio2 = led red
	218	* verify = n ... disable kernel checksum verification for faster booting
	219	*/
	220	#define CONFIG_EXTRA_ENV_SETTINGS \
	221	"tftpdir=calimero\0" \
	222	"flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
	223	"erase 0x60800000 +0x400000; " \
	224	"cp.b $loadaddr 0x60800000 $filesize\0" \
	225	"flashrootfs=" \
	226	"tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
	227	"erase 0x60c00000 +0x2e00000; " \
	228	"cp.b $loadaddr 0x60c00000 $filesize\0" \
	229	"flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
	230	"protect off all; " \
	231	"erase 0x60000000 +0x80000; " \
	232	"cp.b $loadaddr 0x60000000 $filesize\0" \
	233	"flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
	234	"erase 0x60080000 +0x780000; " \
	235	"cp.b $loadaddr 0x60080000 $filesize\0" \
	236	"erase_persistent=erase 0x63a00000 +0x600000;\0" \
	237	"bootnor=setenv bootargs console=ttyS2,115200n8 " \
	238	"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
	239	"rootwait ethaddr=$ethaddr; " \
	240	"gpio c 1; gpio s 2; bootm 0x60800000\0" \
	241	"bootrlk=gpio s 1; gpio s 2;" \
	242	"setenv bootargs console=ttyS2,115200n8 " \
	243	"ethaddr=$ethaddr; bootm 0x60080000\0" \
	244	"boottftp=setenv bootargs console=ttyS2,115200n8 " \
	245	"root=/dev/mtdblock3 rw rootfstype=jffs2 " \
	246	"rootwait ethaddr=$ethaddr; " \
	247	"tftpboot $loadaddr $tftpdir/uImage;" \
	248	"gpio c 1; gpio s 2; bootm $loadaddr\0" \
	249	"checkupdate=if test -n $update_flag; then " \
	250	"echo Previous update failed - starting RLK; " \
	251	"run bootrlk; fi; " \
	252	"if test -n $initial_setup; then " \
	253	"echo Running initial setup procedure; " \
	254	"sleep 1; run flashall; fi\0" \
	255	"product=accessory\0" \
	256	"serial=XX12345\0" \
	257	"checknor=" \
	258	"if gpio i 0; then run bootnor; fi;\0" \
	259	"checkrlk=" \
	260	"if gpio i 0; then run bootrlk; fi;\0" \
	261	"checkbutton=" \
	262	"run checknor; sleep 1;" \
	263	"run checknor; sleep 1;" \
	264	"run checknor; sleep 1;" \
	265	"run checknor; sleep 1;" \
	266	"run checknor;" \
	267	"gpio s 1; gpio s 2;" \
	268	"echo ---- Release button to boot RLK ----;" \
	269	"run checkrlk; sleep 1;" \
	270	"run checkrlk; sleep 1;" \
	271	"run checkrlk; sleep 1;" \
	272	"run checkrlk; sleep 1;" \
	273	"run checkrlk; sleep 1;" \
	274	"run checkrlk;" \
	275	"echo ---- Factory reset requested ----;" \
	276	"gpio c 1;" \
277	"setenv factory_reset true;" \
278	"saveenv;" \
279	"run bootnor;\0" \
280	"flashall=run flashrlk;" \
281	"run flashkernel;" \
282	"run flashrootfs;" \
283	"setenv erase_datafs true;" \
284	"setenv initial_setup;" \
285	"saveenv;" \
286	"run bootnor;\0" \
287	"verify=n\0" \
288	"clearenv=protect off all;" \
289	"erase 0x60040000 +0x40000;\0" \
290	"bootlimit=3\0" \
291	"altbootcmd=run bootrlk\0"
292
293	#define CONFIG_PREBOOT \
294	"echo Version: $ver; " \
295	"echo Serial: $serial; " \
296	"echo MAC: $ethaddr; " \
297	"echo Product: $product; " \
298	"gpio c 1; gpio c 2;"
299
300	/*
301	* U-Boot commands
302	*/
9a3aae22	303	#define CONFIG_CMD_ENV
9a3aae22	304	#define CONFIG_CMD_DIAG
9a3aae22	305	#define CONFIG_CMD_SAVES
9a3aae22 CR	306
9a3aae22 CR	307	#ifndef CONFIG_DRIVER_TI_EMAC
9a3aae22 CR	308	#endif
	309
	310	/* additions for new relocation code, must added to all boards */
	311	#define CONFIG_SYS_SDRAM_BASE 0xc0000000
	312	/* initial stack pointer in internal SRAM */
	313	#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
	314
	315	#define CONFIG_BOOTCOUNT_LIMIT
0044c42e	316	#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
9a3aae22 CR	317	#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
	318
	319	#ifndef __ASSEMBLY__
	320	int calimain_get_osc_freq(void);
	321	#endif
	322
	323	#endif /* __CONFIG_H */