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ns16550: move CONFIG_SYS_NS16550 to Kconfig
[people/ms/u-boot.git] / include / configs / calimain.h
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9a3aae22 1/*
30493aac 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH
9a3aae22
CR		 3 *
4 * Based on da850evm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
9a3aae22
CR		 10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * Board
17 */
18#define CONFIG_DRIVER_TI_EMAC
19#define MACH_TYPE_CALIMAIN 3528
20#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
21
22/*
23 * SoC Configuration
24 */
25#define CONFIG_MACH_DAVINCI_CALIMAIN
9a3aae22
CR		 26#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
27#define CONFIG_SOC_DA850 /* TI DA850 SoC */
28#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
29#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
30#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
31#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
32#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
9a3aae22
CR		 33#define CONFIG_SYS_TEXT_BASE 0x60000000
34#define CONFIG_DA850_LOWLEVEL
35#define CONFIG_SYS_DA850_PLL_INIT
36#define CONFIG_SYS_DA850_DDR_INIT
37#define CONFIG_ARCH_CPU_INIT
38#define CONFIG_DA8XX_GPIO
39#define CONFIG_HW_WATCHDOG
40#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
41#define CONFIG_SYS_WDT_PERIOD_LOW \
42 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
43#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
44#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
45
46/*
47 * PLL configuration
48 */
49#define CONFIG_SYS_DV_CLKMODE 0
50#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
51#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
52#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
53#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
54#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
55#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
56#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
57#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
58
59#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
60#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
61#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
62#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
63
64#define CONFIG_SYS_DA850_PLL0_PLLM \
65 ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
66#define CONFIG_SYS_DA850_PLL1_PLLM \
67 ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
68
69/*
70 * DDR2 memory configuration
71 */
72#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
73 DV_DDR_PHY_EXT_STRBEN | \
74 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
75
76#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
77 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
78 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
79 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
80 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
81 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
82 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
83 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
84 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
85
86/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
87#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
88
89#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
90 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
91 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
92 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
93 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
94 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
95 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
96 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
97 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
98
99#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
100 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
101 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
102 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
103 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
104 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
105 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
106 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
107
108#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
109#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
110
111/*
112 * Flash memory timing
113 */
114
115#define CONFIG_SYS_DA850_CS2CFG ( \
116 DAVINCI_ABCR_WSETUP(2) | \
117 DAVINCI_ABCR_WSTROBE(5) | \
118 DAVINCI_ABCR_WHOLD(3) | \
119 DAVINCI_ABCR_RSETUP(1) | \
120 DAVINCI_ABCR_RSTROBE(14) | \
121 DAVINCI_ABCR_RHOLD(0) | \
122 DAVINCI_ABCR_TA(3) | \
123 DAVINCI_ABCR_ASIZE_16BIT)
124
125/* single 64 MB NOR flash device connected to CS2 and CS3 */
126#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
127
128/*
129 * Memory Info
130 */
131#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
132#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
133#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
134#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
135
136#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
137 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
138 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
139 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
140 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
141 DAVINCI_SYSCFG_SUSPSRC_I2C)
142
143/* memtest start addr */
144#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
145
146/* memtest will be run on 16MB */
147#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
148
149#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
9a3aae22
CR		 150
151/*
152 * Serial Driver info
153 */
9a3aae22
CR		 154#define CONFIG_SYS_NS16550_SERIAL
155#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
156#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
157#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
158#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
159#define CONFIG_BAUDRATE 115200 /* Default baud rate */
9a3aae22
CR		 160
161#define CONFIG_ENV_IS_IN_FLASH
162#define CONFIG_FLASH_CFI_DRIVER
163#define CONFIG_SYS_FLASH_CFI
164#define CONFIG_SYS_FLASH_PROTECTION
165#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
166#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
167#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
168#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
169#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
170#define CONFIG_ENV_ADDR \
171 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
172#define CONFIG_ENV_SIZE (128 << 10)
173#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
174#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
175#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
176#define CONFIG_SYS_MAX_FLASH_SECT \
177 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
178
179/*
180 * Network & Ethernet Configuration
181 */
182#ifdef CONFIG_DRIVER_TI_EMAC
183#define CONFIG_EMAC_MDIO_PHY_NUM 1
184#define CONFIG_MII
9a3aae22
CR		 185#define CONFIG_BOOTP_DNS
186#define CONFIG_BOOTP_DNS2
187#define CONFIG_BOOTP_SEND_HOSTNAME
188#define CONFIG_NET_RETRY_COUNT 10
189#endif
190
191/*
192 * U-Boot general configuration
193 */
194#define CONFIG_BOOTFILE "uImage" /* Boot file name */
9a3aae22
CR		 195#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
196#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
197#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
198#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
199#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
200#define CONFIG_LOADADDR 0xc0700000
201#define CONFIG_VERSION_VARIABLE
202#define CONFIG_AUTO_COMPLETE
203#define CONFIG_SYS_HUSH_PARSER
9a3aae22
CR		 204#define CONFIG_CMDLINE_EDITING
205#define CONFIG_SYS_LONGHELP
206#define CONFIG_CRC32_VERIFY
207#define CONFIG_MX_CYCLIC
208
209/*
210 * Linux Information
211 */
212#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
213#define CONFIG_CMDLINE_TAG
214#define CONFIG_REVISION_TAG
215#define CONFIG_SETUP_MEMORY_TAGS
216#define CONFIG_BOOTARGS ""
217#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
218#define CONFIG_BOOTDELAY 0
219#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
220#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
9a3aae22
CR		 221#define CONFIG_RESET_TO_RETRY
222
223/*
224 * Default environment settings
225 * gpio0 = button, gpio1 = led green, gpio2 = led red
226 * verify = n ... disable kernel checksum verification for faster booting
227 */
228#define CONFIG_EXTRA_ENV_SETTINGS \
229 "tftpdir=calimero\0" \
230 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
231 "erase 0x60800000 +0x400000; " \
232 "cp.b $loadaddr 0x60800000 $filesize\0" \
233 "flashrootfs=" \
234 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
235 "erase 0x60c00000 +0x2e00000; " \
236 "cp.b $loadaddr 0x60c00000 $filesize\0" \
237 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
238 "protect off all; " \
239 "erase 0x60000000 +0x80000; " \
240 "cp.b $loadaddr 0x60000000 $filesize\0" \
241 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
242 "erase 0x60080000 +0x780000; " \
243 "cp.b $loadaddr 0x60080000 $filesize\0" \
244 "erase_persistent=erase 0x63a00000 +0x600000;\0" \
245 "bootnor=setenv bootargs console=ttyS2,115200n8 " \
246 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
247 "rootwait ethaddr=$ethaddr; " \
248 "gpio c 1; gpio s 2; bootm 0x60800000\0" \
249 "bootrlk=gpio s 1; gpio s 2;" \
250 "setenv bootargs console=ttyS2,115200n8 " \
251 "ethaddr=$ethaddr; bootm 0x60080000\0" \
252 "boottftp=setenv bootargs console=ttyS2,115200n8 " \
253 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
254 "rootwait ethaddr=$ethaddr; " \
255 "tftpboot $loadaddr $tftpdir/uImage;" \
256 "gpio c 1; gpio s 2; bootm $loadaddr\0" \
257 "checkupdate=if test -n $update_flag; then " \
258 "echo Previous update failed - starting RLK; " \
259 "run bootrlk; fi; " \
260 "if test -n $initial_setup; then " \
261 "echo Running initial setup procedure; " \
262 "sleep 1; run flashall; fi\0" \
263 "product=accessory\0" \
264 "serial=XX12345\0" \
265 "checknor=" \
266 "if gpio i 0; then run bootnor; fi;\0" \
267 "checkrlk=" \
268 "if gpio i 0; then run bootrlk; fi;\0" \
269 "checkbutton=" \
270 "run checknor; sleep 1;" \
271 "run checknor; sleep 1;" \
272 "run checknor; sleep 1;" \
273 "run checknor; sleep 1;" \
274 "run checknor;" \
275 "gpio s 1; gpio s 2;" \
276 "echo ---- Release button to boot RLK ----;" \
277 "run checkrlk; sleep 1;" \
278 "run checkrlk; sleep 1;" \
279 "run checkrlk; sleep 1;" \
280 "run checkrlk; sleep 1;" \
281 "run checkrlk; sleep 1;" \
282 "run checkrlk;" \
283 "echo ---- Factory reset requested ----;" \
284 "gpio c 1;" \
285 "setenv factory_reset true;" \
286 "saveenv;" \
287 "run bootnor;\0" \
288 "flashall=run flashrlk;" \
289 "run flashkernel;" \
290 "run flashrootfs;" \
291 "setenv erase_datafs true;" \
292 "setenv initial_setup;" \
293 "saveenv;" \
294 "run bootnor;\0" \
295 "verify=n\0" \
296 "clearenv=protect off all;" \
297 "erase 0x60040000 +0x40000;\0" \
298 "bootlimit=3\0" \
299 "altbootcmd=run bootrlk\0"
300
301#define CONFIG_PREBOOT \
302 "echo Version: $ver; " \
303 "echo Serial: $serial; " \
304 "echo MAC: $ethaddr; " \
305 "echo Product: $product; " \
306 "gpio c 1; gpio c 2;"
307
308/*
309 * U-Boot commands
310 */
9a3aae22
CR		 311#define CONFIG_CMD_ENV
312#define CONFIG_CMD_ASKENV
313#define CONFIG_CMD_DHCP
314#define CONFIG_CMD_DIAG
315#define CONFIG_CMD_MII
316#define CONFIG_CMD_PING
317#define CONFIG_CMD_SAVES
9a3aae22
CR		 318
319#ifndef CONFIG_DRIVER_TI_EMAC
9a3aae22
CR		 320#undef CONFIG_CMD_DHCP
321#undef CONFIG_CMD_MII
322#undef CONFIG_CMD_PING
323#endif
324
325/* additions for new relocation code, must added to all boards */
326#define CONFIG_SYS_SDRAM_BASE 0xc0000000
327/* initial stack pointer in internal SRAM */
328#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
329
330#define CONFIG_BOOTCOUNT_LIMIT
0044c42e 331#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
9a3aae22
CR		 332#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
333
334#ifndef __ASSEMBLY__
335int calimain_get_osc_freq(void);
336#endif
337
338#endif /* __CONFIG_H */
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