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Move defaults from config_cmd_default.h to Kconfig
[people/ms/u-boot.git] / include / configs / calimain.h
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9a3aae22 1/*
30493aac 2 * Copyright (C) 2011-2014 OMICRON electronics GmbH
9a3aae22
CR		 3 *
4 * Based on da850evm.h. Original Copyrights follow:
5 *
6 * Copyright (C) 2010 Texas Instruments Incorporated - http://www.ti.com/
7 * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
8 *
1a459660 9 * SPDX-License-Identifier: GPL-2.0+
9a3aae22
CR		 10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * Board
17 */
18#define CONFIG_DRIVER_TI_EMAC
19#define MACH_TYPE_CALIMAIN 3528
20#define CONFIG_MACH_TYPE MACH_TYPE_CALIMAIN
30493aac 21#define CONFIG_SYS_GENERIC_BOARD
9a3aae22
CR		 22
23/*
24 * SoC Configuration
25 */
26#define CONFIG_MACH_DAVINCI_CALIMAIN
9a3aae22
CR		 27#define CONFIG_SOC_DA8XX /* TI DA8xx SoC */
28#define CONFIG_SOC_DA850 /* TI DA850 SoC */
29#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
30#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
31#define CONFIG_SYS_OSCIN_FREQ calimain_get_osc_freq()
32#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
33#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
9a3aae22
CR		 34#define CONFIG_SYS_TEXT_BASE 0x60000000
35#define CONFIG_DA850_LOWLEVEL
36#define CONFIG_SYS_DA850_PLL_INIT
37#define CONFIG_SYS_DA850_DDR_INIT
38#define CONFIG_ARCH_CPU_INIT
39#define CONFIG_DA8XX_GPIO
40#define CONFIG_HW_WATCHDOG
41#define CONFIG_SYS_WDTTIMERBASE DAVINCI_TIMER1_BASE
42#define CONFIG_SYS_WDT_PERIOD_LOW \
43 (60 * CONFIG_SYS_OSCIN_FREQ) /* 60 s heartbeat */
44#define CONFIG_SYS_WDT_PERIOD_HIGH 0x0
45#define CONFIG_SYS_DV_NOR_BOOT_CFG (0x11)
46
47/*
48 * PLL configuration
49 */
50#define CONFIG_SYS_DV_CLKMODE 0
51#define CONFIG_SYS_DA850_PLL0_POSTDIV 1
52#define CONFIG_SYS_DA850_PLL0_PLLDIV1 0x8000
53#define CONFIG_SYS_DA850_PLL0_PLLDIV2 0x8001
54#define CONFIG_SYS_DA850_PLL0_PLLDIV3 0x8002
55#define CONFIG_SYS_DA850_PLL0_PLLDIV4 0x8003
56#define CONFIG_SYS_DA850_PLL0_PLLDIV5 0x8002
57#define CONFIG_SYS_DA850_PLL0_PLLDIV6 CONFIG_SYS_DA850_PLL0_PLLDIV1
58#define CONFIG_SYS_DA850_PLL0_PLLDIV7 0x8005
59
60#define CONFIG_SYS_DA850_PLL1_POSTDIV 1
61#define CONFIG_SYS_DA850_PLL1_PLLDIV1 0x8000
62#define CONFIG_SYS_DA850_PLL1_PLLDIV2 0x8001
63#define CONFIG_SYS_DA850_PLL1_PLLDIV3 0x8002
64
65#define CONFIG_SYS_DA850_PLL0_PLLM \
66 ((calimain_get_osc_freq() == 25000000) ? 23 : 24)
67#define CONFIG_SYS_DA850_PLL1_PLLM \
68 ((calimain_get_osc_freq() == 25000000) ? 20 : 21)
69
70/*
71 * DDR2 memory configuration
72 */
73#define CONFIG_SYS_DA850_DDR2_DDRPHYCR (DV_DDR_PHY_PWRDNEN | \
74 DV_DDR_PHY_EXT_STRBEN | \
75 (0x4 << DV_DDR_PHY_RD_LATENCY_SHIFT))
76
77#define CONFIG_SYS_DA850_DDR2_SDBCR ( \
78 (1 << DV_DDR_SDCR_DDR2EN_SHIFT) | \
79 (1 << DV_DDR_SDCR_DDRDRIVE0_SHIFT) | \
80 (1 << DV_DDR_SDCR_DDREN_SHIFT) | \
81 (1 << DV_DDR_SDCR_SDRAMEN_SHIFT) | \
82 (1 << DV_DDR_SDCR_BUS_WIDTH_SHIFT) | \
83 (0x3 << DV_DDR_SDCR_CL_SHIFT) | \
84 (0x3 << DV_DDR_SDCR_IBANK_SHIFT) | \
85 (0x2 << DV_DDR_SDCR_PAGESIZE_SHIFT))
86
87/* SDBCR2 is only used if IBANK_POS bit in SDBCR is set */
88#define CONFIG_SYS_DA850_DDR2_SDBCR2 0
89
90#define CONFIG_SYS_DA850_DDR2_SDTIMR ( \
91 (16 << DV_DDR_SDTMR1_RFC_SHIFT) | \
92 (1 << DV_DDR_SDTMR1_RP_SHIFT) | \
93 (1 << DV_DDR_SDTMR1_RCD_SHIFT) | \
94 (1 << DV_DDR_SDTMR1_WR_SHIFT) | \
95 (5 << DV_DDR_SDTMR1_RAS_SHIFT) | \
96 (7 << DV_DDR_SDTMR1_RC_SHIFT) | \
97 (1 << DV_DDR_SDTMR1_RRD_SHIFT) | \
98 (1 << DV_DDR_SDTMR1_WTR_SHIFT))
99
100#define CONFIG_SYS_DA850_DDR2_SDTIMR2 ( \
101 (7 << DV_DDR_SDTMR2_RASMAX_SHIFT) | \
102 (2 << DV_DDR_SDTMR2_XP_SHIFT) | \
103 (0 << DV_DDR_SDTMR2_ODT_SHIFT) | \
104 (18 << DV_DDR_SDTMR2_XSNR_SHIFT) | \
105 (199 << DV_DDR_SDTMR2_XSRD_SHIFT) | \
106 (0 << DV_DDR_SDTMR2_RTP_SHIFT) | \
107 (2 << DV_DDR_SDTMR2_CKE_SHIFT))
108
109#define CONFIG_SYS_DA850_DDR2_SDRCR 0x000003FF
110#define CONFIG_SYS_DA850_DDR2_PBBPR 0x30
111
112/*
113 * Flash memory timing
114 */
115
116#define CONFIG_SYS_DA850_CS2CFG ( \
117 DAVINCI_ABCR_WSETUP(2) | \
118 DAVINCI_ABCR_WSTROBE(5) | \
119 DAVINCI_ABCR_WHOLD(3) | \
120 DAVINCI_ABCR_RSETUP(1) | \
121 DAVINCI_ABCR_RSTROBE(14) | \
122 DAVINCI_ABCR_RHOLD(0) | \
123 DAVINCI_ABCR_TA(3) | \
124 DAVINCI_ABCR_ASIZE_16BIT)
125
126/* single 64 MB NOR flash device connected to CS2 and CS3 */
127#define CONFIG_SYS_DA850_CS3CFG CONFIG_SYS_DA850_CS2CFG
128
129/*
130 * Memory Info
131 */
132#define CONFIG_SYS_MALLOC_LEN (0x10000 + 1*1024*1024) /* malloc() len */
133#define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */
134#define PHYS_SDRAM_1_SIZE (128 << 20) /* SDRAM size 128MB */
135#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/
136
137#define CONFIG_SYS_DA850_SYSCFG_SUSPSRC ( \
138 DAVINCI_SYSCFG_SUSPSRC_TIMER0 | \
139 DAVINCI_SYSCFG_SUSPSRC_SPI1 | \
140 DAVINCI_SYSCFG_SUSPSRC_UART2 | \
141 DAVINCI_SYSCFG_SUSPSRC_EMAC | \
142 DAVINCI_SYSCFG_SUSPSRC_I2C)
143
144/* memtest start addr */
145#define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000)
146
147/* memtest will be run on 16MB */
148#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (16 << 20))
149
150#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
9a3aae22
CR		 151
152/*
153 * Serial Driver info
154 */
155#define CONFIG_SYS_NS16550
156#define CONFIG_SYS_NS16550_SERIAL
157#define CONFIG_SYS_NS16550_REG_SIZE -4 /* NS16550 register size */
158#define CONFIG_SYS_NS16550_COM1 DAVINCI_UART2_BASE /* Base address of UART2 */
159#define CONFIG_SYS_NS16550_CLK clk_get(DAVINCI_UART2_CLKID)
160#define CONFIG_CONS_INDEX 1 /* use UART0 for console */
161#define CONFIG_BAUDRATE 115200 /* Default baud rate */
9a3aae22
CR		 162
163#define CONFIG_ENV_IS_IN_FLASH
164#define CONFIG_FLASH_CFI_DRIVER
165#define CONFIG_SYS_FLASH_CFI
166#define CONFIG_SYS_FLASH_PROTECTION
167#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of flash banks */
169#define CONFIG_SYS_FLASH_SECT_SZ (128 << 10) /* 128KB */
170#define CONFIG_SYS_FLASH_BASE DAVINCI_ASYNC_EMIF_DATA_CE2_BASE
171#define CONFIG_ENV_SECT_SIZE CONFIG_SYS_FLASH_SECT_SZ
172#define CONFIG_ENV_ADDR \
173 (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SECT_SZ * 2)
174#define CONFIG_ENV_SIZE (128 << 10)
175#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
176#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
177#define PHYS_FLASH_SIZE (64 << 20) /* Flash size 64MB */
178#define CONFIG_SYS_MAX_FLASH_SECT \
179 ((PHYS_FLASH_SIZE/CONFIG_SYS_FLASH_SECT_SZ) + 3)
180
181/*
182 * Network & Ethernet Configuration
183 */
184#ifdef CONFIG_DRIVER_TI_EMAC
185#define CONFIG_EMAC_MDIO_PHY_NUM 1
186#define CONFIG_MII
9a3aae22
CR		 187#define CONFIG_BOOTP_DNS
188#define CONFIG_BOOTP_DNS2
189#define CONFIG_BOOTP_SEND_HOSTNAME
190#define CONFIG_NET_RETRY_COUNT 10
191#endif
192
193/*
194 * U-Boot general configuration
195 */
196#define CONFIG_BOOTFILE "uImage" /* Boot file name */
197#define CONFIG_SYS_PROMPT "Calimain > " /* Command Prompt */
198#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
199#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
200#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
201#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Args Buffer Size */
202#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x700000)
203#define CONFIG_LOADADDR 0xc0700000
204#define CONFIG_VERSION_VARIABLE
205#define CONFIG_AUTO_COMPLETE
206#define CONFIG_SYS_HUSH_PARSER
9a3aae22
CR		 207#define CONFIG_CMDLINE_EDITING
208#define CONFIG_SYS_LONGHELP
209#define CONFIG_CRC32_VERIFY
210#define CONFIG_MX_CYCLIC
211
212/*
213 * Linux Information
214 */
215#define LINUX_BOOT_PARAM_ADDR (PHYS_SDRAM_1 + 0x100)
216#define CONFIG_CMDLINE_TAG
217#define CONFIG_REVISION_TAG
218#define CONFIG_SETUP_MEMORY_TAGS
219#define CONFIG_BOOTARGS ""
220#define CONFIG_BOOTCOMMAND "run checkupdate; run checkbutton;"
221#define CONFIG_BOOTDELAY 0
222#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
223#define CONFIG_BOOT_RETRY_TIME 60 /* continue boot after 60 s inactivity */
9a3aae22
CR		 224#define CONFIG_RESET_TO_RETRY
225
226/*
227 * Default environment settings
228 * gpio0 = button, gpio1 = led green, gpio2 = led red
229 * verify = n ... disable kernel checksum verification for faster booting
230 */
231#define CONFIG_EXTRA_ENV_SETTINGS \
232 "tftpdir=calimero\0" \
233 "flashkernel=tftpboot $loadaddr $tftpdir/uImage; " \
234 "erase 0x60800000 +0x400000; " \
235 "cp.b $loadaddr 0x60800000 $filesize\0" \
236 "flashrootfs=" \
237 "tftpboot $loadaddr $tftpdir/rootfs.jffs2; " \
238 "erase 0x60c00000 +0x2e00000; " \
239 "cp.b $loadaddr 0x60c00000 $filesize\0" \
240 "flashuboot=tftpboot $loadaddr $tftpdir/u-boot.bin; " \
241 "protect off all; " \
242 "erase 0x60000000 +0x80000; " \
243 "cp.b $loadaddr 0x60000000 $filesize\0" \
244 "flashrlk=tftpboot $loadaddr $tftpdir/uImage-rlk; " \
245 "erase 0x60080000 +0x780000; " \
246 "cp.b $loadaddr 0x60080000 $filesize\0" \
247 "erase_persistent=erase 0x63a00000 +0x600000;\0" \
248 "bootnor=setenv bootargs console=ttyS2,115200n8 " \
249 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
250 "rootwait ethaddr=$ethaddr; " \
251 "gpio c 1; gpio s 2; bootm 0x60800000\0" \
252 "bootrlk=gpio s 1; gpio s 2;" \
253 "setenv bootargs console=ttyS2,115200n8 " \
254 "ethaddr=$ethaddr; bootm 0x60080000\0" \
255 "boottftp=setenv bootargs console=ttyS2,115200n8 " \
256 "root=/dev/mtdblock3 rw rootfstype=jffs2 " \
257 "rootwait ethaddr=$ethaddr; " \
258 "tftpboot $loadaddr $tftpdir/uImage;" \
259 "gpio c 1; gpio s 2; bootm $loadaddr\0" \
260 "checkupdate=if test -n $update_flag; then " \
261 "echo Previous update failed - starting RLK; " \
262 "run bootrlk; fi; " \
263 "if test -n $initial_setup; then " \
264 "echo Running initial setup procedure; " \
265 "sleep 1; run flashall; fi\0" \
266 "product=accessory\0" \
267 "serial=XX12345\0" \
268 "checknor=" \
269 "if gpio i 0; then run bootnor; fi;\0" \
270 "checkrlk=" \
271 "if gpio i 0; then run bootrlk; fi;\0" \
272 "checkbutton=" \
273 "run checknor; sleep 1;" \
274 "run checknor; sleep 1;" \
275 "run checknor; sleep 1;" \
276 "run checknor; sleep 1;" \
277 "run checknor;" \
278 "gpio s 1; gpio s 2;" \
279 "echo ---- Release button to boot RLK ----;" \
280 "run checkrlk; sleep 1;" \
281 "run checkrlk; sleep 1;" \
282 "run checkrlk; sleep 1;" \
283 "run checkrlk; sleep 1;" \
284 "run checkrlk; sleep 1;" \
285 "run checkrlk;" \
286 "echo ---- Factory reset requested ----;" \
287 "gpio c 1;" \
288 "setenv factory_reset true;" \
289 "saveenv;" \
290 "run bootnor;\0" \
291 "flashall=run flashrlk;" \
292 "run flashkernel;" \
293 "run flashrootfs;" \
294 "setenv erase_datafs true;" \
295 "setenv initial_setup;" \
296 "saveenv;" \
297 "run bootnor;\0" \
298 "verify=n\0" \
299 "clearenv=protect off all;" \
300 "erase 0x60040000 +0x40000;\0" \
301 "bootlimit=3\0" \
302 "altbootcmd=run bootrlk\0"
303
304#define CONFIG_PREBOOT \
305 "echo Version: $ver; " \
306 "echo Serial: $serial; " \
307 "echo MAC: $ethaddr; " \
308 "echo Product: $product; " \
309 "gpio c 1; gpio c 2;"
310
311/*
312 * U-Boot commands
313 */
9a3aae22
CR		 314#define CONFIG_CMD_ENV
315#define CONFIG_CMD_ASKENV
316#define CONFIG_CMD_DHCP
317#define CONFIG_CMD_DIAG
318#define CONFIG_CMD_MII
319#define CONFIG_CMD_PING
320#define CONFIG_CMD_SAVES
9a3aae22
CR		 321#define CONFIG_CMD_GPIO
322
323#ifndef CONFIG_DRIVER_TI_EMAC
9a3aae22
CR		 324#undef CONFIG_CMD_DHCP
325#undef CONFIG_CMD_MII
326#undef CONFIG_CMD_PING
327#endif
328
329/* additions for new relocation code, must added to all boards */
330#define CONFIG_SYS_SDRAM_BASE 0xc0000000
331/* initial stack pointer in internal SRAM */
332#define CONFIG_SYS_INIT_SP_ADDR (0x8001ff00)
333
334#define CONFIG_BOOTCOUNT_LIMIT
0044c42e 335#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
9a3aae22
CR		 336#define CONFIG_SYS_BOOTCOUNT_ADDR DAVINCI_RTC_BASE
337
338#ifndef __ASSEMBLY__
339int calimain_get_osc_freq(void);
340#endif
341
342#endif /* __CONFIG_H */
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