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1/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
b2a6dfe4 16#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
53677ef1 17#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
ab9f5f83 18#define CONFIG_DISPLAY_BOARDINFO
5e5f9ed2 19
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20/*
21 * allowed and functional CONFIG_SYS_TEXT_BASE values:
22 * 0xfe000000 low boot at 0x00000100 (default board setting)
23 * 0x00100000 RAM load and test
24 */
25#define CONFIG_SYS_TEXT_BASE 0xFE000000
26
6d0f6bcf 27#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e5f9ed2 28
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29#define CONFIG_BOARD_EARLY_INIT_R
30
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31#define CONFIG_HIGH_BATS 1 /* High BATs supported */
32
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33/*
34 * Serial console configuration
35 */
36#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
37#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
6d0f6bcf 38#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e5f9ed2 39
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40/*
41 * BOOTP options
42 */
43#define CONFIG_BOOTP_BOOTFILESIZE
44#define CONFIG_BOOTP_BOOTPATH
45#define CONFIG_BOOTP_GATEWAY
46#define CONFIG_BOOTP_HOSTNAME
47
5e5f9ed2 48/*
37e4f24b 49 * Command line configuration.
5e5f9ed2 50 */
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51#define CONFIG_CMD_ASKENV
52#define CONFIG_CMD_DATE
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53#define CONFIG_CMD_IMMAP
54#define CONFIG_CMD_MII
37e4f24b 55#define CONFIG_CMD_REGINFO
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56
57/*
58 * MUST be low boot - HIGHBOOT is not supported anymore
59 */
14d0a02a 60#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
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61# define CONFIG_SYS_LOWBOOT 1
62# define CONFIG_SYS_LOWBOOT16 1
5e5f9ed2 63#else
14d0a02a 64# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
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65#endif
66
67/*
68 * Autobooting
69 */
70#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
71
72#define CONFIG_PREBOOT "echo;" \
32bf3d14 73 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
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74 "echo"
75
76#undef CONFIG_BOOTARGS
77
78#define CONFIG_EXTRA_ENV_SETTINGS \
79 "netdev=eth0\0" \
80 "nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b 81 "nfsroot=${serverip}:${rootpath}\0" \
5e5f9ed2 82 "ramargs=setenv bootargs root=/dev/ram rw\0" \
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83 "addip=setenv bootargs ${bootargs} " \
84 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
85 ":${hostname}:${netdev}:off panic=1\0" \
5e5f9ed2 86 "flash_nfs=run nfsargs addip;" \
fe126d8b 87 "bootm ${kernel_addr}\0" \
5e5f9ed2 88 "flash_self=run ramargs addip;" \
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89 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
90 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
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91 "rootpath=/opt/eldk/ppc_6xx\0" \
92 "bootfile=/tftpboot/canmb/uImage\0" \
93 ""
94
95#define CONFIG_BOOTCOMMAND "run flash_self"
96
97/*
98 * IPB Bus clocking configuration.
99 */
6d0f6bcf 100#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
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101
102/*
103 * Flash configuration, expect one 16 Megabyte Bank at most
104 */
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105#define CONFIG_SYS_FLASH_BASE 0xFE000000
106#define CONFIG_SYS_FLASH_SIZE 0x02000000
107#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
108#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
5e5f9ed2 109
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110#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
111#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e5f9ed2 112
00b1883a 113#define CONFIG_FLASH_CFI_DRIVER
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114#define CONFIG_SYS_FLASH_CFI
115#define CONFIG_SYS_FLASH_EMPTY_INFO
5e5f9ed2 116
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117/*
118 * Environment settings
119 */
5a1aceb0 120#define CONFIG_ENV_IS_IN_FLASH 1
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121#define CONFIG_ENV_OFFSET (2*128*1024)
122#define CONFIG_ENV_SIZE 0x2000
123#define CONFIG_ENV_SECT_SIZE (128*1024)
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124
125/*
126 * Memory map
127 *
128 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
129 */
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130#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
131#define CONFIG_SYS_SDRAM_BASE 0x00000000
132#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
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133
134/* Use SRAM until RAM will be available */
6d0f6bcf 135#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982 136#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
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137
138
25ddd1fb 139#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 140#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e5f9ed2 141
14d0a02a 142#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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143#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
144# define CONFIG_SYS_RAMBOOT 1
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145#endif
146
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147#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
148#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
149#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
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150
151/*
152 * Ethernet configuration
153 */
154#define CONFIG_MPC5xxx_FEC 1
86321fc1 155#define CONFIG_MPC5xxx_FEC_MII100
a6310928 156#define CONFIG_PHY_ADDR 0x0
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157/*
158 * GPIO configuration:
159 * PSC1,2,3 predefined as UART
160 * PCI disabled
161 * Ethernet 100 with MD
162 */
6d0f6bcf 163#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444
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164
165/*
166 * Miscellaneous configurable options
167 */
6d0f6bcf 168#define CONFIG_SYS_LONGHELP /* undef to save memory */
37e4f24b 169#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 170# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e5f9ed2 171#else
6d0f6bcf 172# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e5f9ed2 173#endif
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174#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
175#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
176#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e5f9ed2 177
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178#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
179#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
5e5f9ed2 180
6d0f6bcf 181#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
5e5f9ed2 182
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183#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
184
6d0f6bcf 185#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
37e4f24b 186#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 187# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
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188#endif
189
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190/*
191 * Various low-level settings
192 */
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193#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
194#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e5f9ed2 195
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196#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
197#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
198#define CONFIG_SYS_BOOTCS_CFG 0x00047D01
199#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
200#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e5f9ed2 201
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202#define CONFIG_SYS_CS_BURST 0x00000000
203#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e5f9ed2 204
6d0f6bcf 205#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
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206
207#endif /* __CONFIG_H */