]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/canmb.h
cmd: add Kconfig option for 'date' command
[people/ms/u-boot.git] / include / configs / canmb.h
CommitLineData
5e5f9ed2
WD
1/*
2 * (C) Copyright 2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
3765b3e7 5 * SPDX-License-Identifier: GPL-2.0+
5e5f9ed2
WD
6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11/*
12 * High Level Configuration Options
13 * (easy to change)
14 */
15
b2a6dfe4 16#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */
53677ef1 17#define CONFIG_CANMB 1 /* ... on canmb board - we need this for FEC.C */
5e5f9ed2 18
2ae18241
WD
19/*
20 * allowed and functional CONFIG_SYS_TEXT_BASE values:
21 * 0xfe000000 low boot at 0x00000100 (default board setting)
22 * 0x00100000 RAM load and test
23 */
24#define CONFIG_SYS_TEXT_BASE 0xFE000000
25
6d0f6bcf 26#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
5e5f9ed2 27
5e5f9ed2
WD
28#define CONFIG_BOARD_EARLY_INIT_R
29
31d82672
BB
30#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31
5e5f9ed2
WD
32/*
33 * Serial console configuration
34 */
35#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
6d0f6bcf 36#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
5e5f9ed2 37
80ff4f99
JL
38/*
39 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
5e5f9ed2 46/*
37e4f24b 47 * Command line configuration.
5e5f9ed2 48 */
37e4f24b 49#define CONFIG_CMD_IMMAP
37e4f24b 50#define CONFIG_CMD_REGINFO
5e5f9ed2
WD
51
52/*
53 * MUST be low boot - HIGHBOOT is not supported anymore
54 */
14d0a02a 55#if (CONFIG_SYS_TEXT_BASE == 0xFE000000) /* Boot low with 32 MB Flash */
6d0f6bcf
JCPV
56# define CONFIG_SYS_LOWBOOT 1
57# define CONFIG_SYS_LOWBOOT16 1
5e5f9ed2 58#else
14d0a02a 59# error "CONFIG_SYS_TEXT_BASE must be 0xFE000000"
5e5f9ed2
WD
60#endif
61
62/*
63 * Autobooting
64 */
5e5f9ed2
WD
65
66#define CONFIG_PREBOOT "echo;" \
32bf3d14 67 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
5e5f9ed2
WD
68 "echo"
69
70#undef CONFIG_BOOTARGS
71
72#define CONFIG_EXTRA_ENV_SETTINGS \
73 "netdev=eth0\0" \
74 "nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b 75 "nfsroot=${serverip}:${rootpath}\0" \
5e5f9ed2 76 "ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b
WD
77 "addip=setenv bootargs ${bootargs} " \
78 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
79 ":${hostname}:${netdev}:off panic=1\0" \
5e5f9ed2 80 "flash_nfs=run nfsargs addip;" \
fe126d8b 81 "bootm ${kernel_addr}\0" \
5e5f9ed2 82 "flash_self=run ramargs addip;" \
fe126d8b
WD
83 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
84 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
5e5f9ed2
WD
85 "rootpath=/opt/eldk/ppc_6xx\0" \
86 "bootfile=/tftpboot/canmb/uImage\0" \
87 ""
88
89#define CONFIG_BOOTCOMMAND "run flash_self"
90
91/*
92 * IPB Bus clocking configuration.
93 */
6d0f6bcf 94#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
5e5f9ed2
WD
95
96/*
97 * Flash configuration, expect one 16 Megabyte Bank at most
98 */
6d0f6bcf
JCPV
99#define CONFIG_SYS_FLASH_BASE 0xFE000000
100#define CONFIG_SYS_FLASH_SIZE 0x02000000
101#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
102#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
5e5f9ed2 103
6d0f6bcf
JCPV
104#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
105#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
5e5f9ed2 106
00b1883a 107#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf
JCPV
108#define CONFIG_SYS_FLASH_CFI
109#define CONFIG_SYS_FLASH_EMPTY_INFO
5e5f9ed2 110
5e5f9ed2
WD
111/*
112 * Environment settings
113 */
5a1aceb0 114#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586
JCPV
115#define CONFIG_ENV_OFFSET (2*128*1024)
116#define CONFIG_ENV_SIZE 0x2000
117#define CONFIG_ENV_SECT_SIZE (128*1024)
5e5f9ed2
WD
118
119/*
120 * Memory map
121 *
122 * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
123 */
6d0f6bcf
JCPV
124#define CONFIG_SYS_MBAR 0xf0000000 /* DO NOT CHANGE this */
125#define CONFIG_SYS_SDRAM_BASE 0x00000000
126#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
5e5f9ed2
WD
127
128/* Use SRAM until RAM will be available */
6d0f6bcf 129#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
553f0982 130#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */
5e5f9ed2 131
25ddd1fb 132#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 133#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
5e5f9ed2 134
14d0a02a 135#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf
JCPV
136#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
137# define CONFIG_SYS_RAMBOOT 1
5e5f9ed2
WD
138#endif
139
6d0f6bcf
JCPV
140#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
141#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
142#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
5e5f9ed2
WD
143
144/*
145 * Ethernet configuration
146 */
147#define CONFIG_MPC5xxx_FEC 1
86321fc1 148#define CONFIG_MPC5xxx_FEC_MII100
a6310928 149#define CONFIG_PHY_ADDR 0x0
5e5f9ed2
WD
150/*
151 * GPIO configuration:
152 * PSC1,2,3 predefined as UART
153 * PCI disabled
154 * Ethernet 100 with MD
155 */
6d0f6bcf 156#define CONFIG_SYS_GPS_PORT_CONFIG 0x00058444
5e5f9ed2
WD
157
158/*
159 * Miscellaneous configurable options
160 */
6d0f6bcf 161#define CONFIG_SYS_LONGHELP /* undef to save memory */
37e4f24b 162#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 163# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
5e5f9ed2 164#else
6d0f6bcf 165# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
5e5f9ed2 166#endif
6d0f6bcf
JCPV
167#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
168#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
169#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
5e5f9ed2 170
6d0f6bcf
JCPV
171#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
172#define CONFIG_SYS_MEMTEST_END 0x01f00000 /* 1 ... 31 MB in DRAM */
5e5f9ed2 173
6d0f6bcf 174#define CONFIG_SYS_LOAD_ADDR 0x200000 /* default load address */
5e5f9ed2 175
5e5f9ed2
WD
176#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
177
6d0f6bcf 178#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
37e4f24b 179#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 180# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
37e4f24b
JL
181#endif
182
5e5f9ed2
WD
183/*
184 * Various low-level settings
185 */
6d0f6bcf
JCPV
186#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
187#define CONFIG_SYS_HID0_FINAL HID0_ICE
5e5f9ed2 188
6d0f6bcf
JCPV
189#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
190#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
191#define CONFIG_SYS_BOOTCS_CFG 0x00047D01
192#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
193#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
5e5f9ed2 194
6d0f6bcf
JCPV
195#define CONFIG_SYS_CS_BURST 0x00000000
196#define CONFIG_SYS_CS_DEADCYCLE 0x33333333
5e5f9ed2 197
6d0f6bcf 198#define CONFIG_SYS_RESET_ADDRESS 0x7f000000
5e5f9ed2
WD
199
200#endif /* __CONFIG_H */