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9b75bad0 SL |
1 | /* |
2 | * | |
3 | * Congatec Conga-QEVAl board configuration file. | |
4 | * | |
5 | * Copyright (C) 2010-2011 Freescale Semiconductor, Inc. | |
6 | * Based on Freescale i.MX6Q Sabre Lite board configuration file. | |
7 | * Copyright (C) 2013, Adeneo Embedded <www.adeneo-embedded.com> | |
8 | * Leo Sartre, <lsartre@adeneo-embedded.com> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
9b75bad0 SL |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_CGTQMX6EVAL_H | |
14 | #define __CONFIG_CGTQMX6EVAL_H | |
15 | ||
9b75bad0 SL |
16 | #include "mx6_common.h" |
17 | ||
9b75bad0 SL |
18 | #define CONFIG_MACH_TYPE 4122 |
19 | ||
d7140351 OS |
20 | #ifdef CONFIG_SPL |
21 | #define CONFIG_SPL_LIBCOMMON_SUPPORT | |
22 | #define CONFIG_SPL_MMC_SUPPORT | |
23 | #define CONFIG_SPL_SPI_SUPPORT | |
24 | #define CONFIG_SPL_SPI_FLASH_SUPPORT | |
25 | #define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024) | |
26 | #define CONFIG_SPL_SPI_LOAD | |
27 | #include "imx6_spl.h" | |
28 | #endif | |
29 | ||
9b75bad0 SL |
30 | /* Size of malloc() pool */ |
31 | #define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024) | |
32 | ||
33 | #define CONFIG_BOARD_EARLY_INIT_F | |
d7140351 | 34 | #define CONFIG_BOARD_LATE_INIT |
9b75bad0 | 35 | #define CONFIG_MISC_INIT_R |
9b75bad0 SL |
36 | |
37 | #define CONFIG_MXC_UART | |
38 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
39 | ||
40 | /* MMC Configs */ | |
9b75bad0 SL |
41 | #define CONFIG_SYS_FSL_ESDHC_ADDR 0 |
42 | ||
71bcdafe | 43 | /* SPI NOR */ |
71bcdafe OS |
44 | #define CONFIG_SPI_FLASH |
45 | #define CONFIG_SPI_FLASH_STMICRO | |
46 | #define CONFIG_SPI_FLASH_SST | |
47 | #define CONFIG_MXC_SPI | |
48 | #define CONFIG_SF_DEFAULT_BUS 0 | |
49 | #define CONFIG_SF_DEFAULT_SPEED 20000000 | |
50 | #define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) | |
51 | ||
9b75bad0 SL |
52 | /* Miscellaneous commands */ |
53 | #define CONFIG_CMD_BMODE | |
54 | ||
862187b7 | 55 | /* Thermal support */ |
1368f993 | 56 | #define CONFIG_IMX_THERMAL |
862187b7 | 57 | |
4c9929d6 | 58 | /* I2C Configs */ |
4c9929d6 OS |
59 | #define CONFIG_SYS_I2C |
60 | #define CONFIG_SYS_I2C_MXC | |
03544c66 AA |
61 | #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ |
62 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ | |
4c9929d6 OS |
63 | #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ |
64 | #define CONFIG_SYS_I2C_SPEED 100000 | |
65 | ||
66 | /* PMIC */ | |
67 | #define CONFIG_POWER | |
68 | #define CONFIG_POWER_I2C | |
69 | #define CONFIG_POWER_PFUZE100 | |
70 | #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 | |
71 | ||
95246ac7 | 72 | /* USB Configs */ |
95246ac7 OS |
73 | #define CONFIG_USB_EHCI |
74 | #define CONFIG_USB_EHCI_MX6 | |
75 | #define CONFIG_USB_STORAGE | |
76 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
77 | #define CONFIG_USB_HOST_ETHER | |
78 | #define CONFIG_USB_ETHER_ASIX | |
79 | #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) | |
80 | #define CONFIG_MXC_USB_FLAGS 0 | |
81 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ | |
82 | #define CONFIG_USB_KEYBOARD | |
83 | #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP | |
84 | ||
3e08e1b7 | 85 | #define CONFIG_USBD_HS |
3e08e1b7 | 86 | |
3e08e1b7 | 87 | #define CONFIG_USB_FUNCTION_MASS_STORAGE |
3e08e1b7 | 88 | |
e0a352d1 | 89 | /* USB Device Firmware Update support */ |
e0a352d1 OS |
90 | #define CONFIG_USB_FUNCTION_DFU |
91 | #define CONFIG_DFU_MMC | |
92 | #define CONFIG_DFU_SF | |
93 | ||
eb76f13a OS |
94 | #define CONFIG_USB_FUNCTION_FASTBOOT |
95 | #define CONFIG_CMD_FASTBOOT | |
96 | #define CONFIG_ANDROID_BOOT_IMAGE | |
97 | #define CONFIG_FASTBOOT_BUF_ADDR CONFIG_SYS_LOAD_ADDR | |
98 | #define CONFIG_FASTBOOT_BUF_SIZE 0x07000000 | |
99 | ||
6d551f27 OS |
100 | /* Framebuffer */ |
101 | #define CONFIG_VIDEO | |
102 | #define CONFIG_VIDEO_IPUV3 | |
103 | #define CONFIG_CFB_CONSOLE | |
104 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
105 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
106 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
107 | #define CONFIG_VIDEO_BMP_RLE8 | |
108 | #define CONFIG_SPLASH_SCREEN | |
109 | #define CONFIG_SPLASH_SCREEN_ALIGN | |
110 | #define CONFIG_BMP_16BPP | |
111 | #define CONFIG_VIDEO_LOGO | |
112 | #define CONFIG_VIDEO_BMP_LOGO | |
113 | #ifdef CONFIG_MX6DL | |
114 | #define CONFIG_IPUV3_CLK 198000000 | |
115 | #else | |
116 | #define CONFIG_IPUV3_CLK 264000000 | |
117 | #endif | |
118 | #define CONFIG_IMX_HDMI | |
119 | ||
6731bc8d OS |
120 | /* SATA */ |
121 | #define CONFIG_CMD_SATA | |
122 | #define CONFIG_DWC_AHSATA | |
123 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
124 | #define CONFIG_DWC_AHSATA_PORT_ID 0 | |
125 | #define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR | |
126 | #define CONFIG_LBA48 | |
127 | #define CONFIG_LIBATA | |
128 | ||
f0222902 | 129 | /* Ethernet */ |
f0222902 OS |
130 | #define CONFIG_FEC_MXC |
131 | #define CONFIG_MII | |
132 | #define IMX_FEC_BASE ENET_BASE_ADDR | |
133 | #define CONFIG_FEC_XCV_TYPE RGMII | |
134 | #define CONFIG_ETHPRIME "FEC" | |
135 | #define CONFIG_FEC_MXC_PHYADDR 6 | |
136 | #define CONFIG_PHYLIB | |
137 | #define CONFIG_PHY_ATHEROS | |
138 | ||
5b94ce2c OS |
139 | /* Command definition */ |
140 | ||
141 | #define CONFIG_MXC_UART_BASE UART2_BASE | |
142 | #define CONFIG_CONSOLE_DEV "ttymxc1" | |
143 | #define CONFIG_MMCROOT "/dev/mmcblk0p2" | |
144 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
9b75bad0 | 145 | |
d7140351 | 146 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
9b75bad0 SL |
147 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
148 | "script=boot.scr\0" \ | |
4ac0c2bf | 149 | "image=zImage\0" \ |
d7140351 | 150 | "fdtfile=undefined\0" \ |
5b94ce2c | 151 | "fdt_addr_r=0x18000000\0" \ |
9b75bad0 | 152 | "boot_fdt=try\0" \ |
5b94ce2c OS |
153 | "ip_dyn=yes\0" \ |
154 | "console=" CONFIG_CONSOLE_DEV "\0" \ | |
e0a352d1 OS |
155 | "dfuspi=dfu 0 sf 0:0:10000000:0\0" \ |
156 | "dfu_alt_info_spl=spl raw 0x400\0" \ | |
157 | "dfu_alt_info_img=u-boot raw 0x10000\0" \ | |
158 | "dfu_alt_info=spl raw 0x400\0" \ | |
5b94ce2c OS |
159 | "bootm_size=0x10000000\0" \ |
160 | "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ | |
9b75bad0 | 161 | "mmcpart=1\0" \ |
5b94ce2c OS |
162 | "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ |
163 | "update_sd_firmware=" \ | |
164 | "if test ${ip_dyn} = yes; then " \ | |
165 | "setenv get_cmd dhcp; " \ | |
166 | "else " \ | |
167 | "setenv get_cmd tftp; " \ | |
168 | "fi; " \ | |
169 | "if mmc dev ${mmcdev}; then " \ | |
170 | "if ${get_cmd} ${update_sd_firmware_filename}; then " \ | |
171 | "setexpr fw_sz ${filesize} / 0x200; " \ | |
172 | "setexpr fw_sz ${fw_sz} + 1; " \ | |
173 | "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ | |
174 | "fi; " \ | |
175 | "fi\0" \ | |
9b75bad0 SL |
176 | "mmcargs=setenv bootargs console=${console},${baudrate} " \ |
177 | "root=${mmcroot}\0" \ | |
178 | "loadbootscript=" \ | |
5b94ce2c | 179 | "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ |
9b75bad0 SL |
180 | "bootscript=echo Running bootscript from mmc ...; " \ |
181 | "source\0" \ | |
5b94ce2c OS |
182 | "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ |
183 | "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ | |
9b75bad0 SL |
184 | "mmcboot=echo Booting from mmc ...; " \ |
185 | "run mmcargs; " \ | |
186 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
187 | "if run loadfdt; then " \ | |
5b94ce2c OS |
188 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ |
189 | "else " \ | |
190 | "if test ${boot_fdt} = try; then " \ | |
191 | "bootz; " \ | |
192 | "else " \ | |
193 | "echo WARN: Cannot load the DT; " \ | |
194 | "fi; " \ | |
195 | "fi; " \ | |
196 | "else " \ | |
197 | "bootz; " \ | |
198 | "fi;\0" \ | |
d7140351 OS |
199 | "findfdt="\ |
200 | "if test $board_rev = MX6Q ; then " \ | |
201 | "setenv fdtfile imx6q-qmx6.dtb; fi; " \ | |
202 | "if test $board_rev = MX6DL ; then " \ | |
203 | "setenv fdtfile imx6dl-qmx6.dtb; fi; " \ | |
204 | "if test $fdtfile = undefined; then " \ | |
205 | "echo WARNING: Could not determine dtb to use; fi; \0" \ | |
5b94ce2c OS |
206 | "netargs=setenv bootargs console=${console},${baudrate} " \ |
207 | "root=/dev/nfs " \ | |
208 | "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ | |
209 | "netboot=echo Booting from net ...; " \ | |
210 | "run netargs; " \ | |
211 | "if test ${ip_dyn} = yes; then " \ | |
212 | "setenv get_cmd dhcp; " \ | |
213 | "else " \ | |
214 | "setenv get_cmd tftp; " \ | |
215 | "fi; " \ | |
216 | "${get_cmd} ${image}; " \ | |
217 | "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ | |
218 | "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ | |
219 | "bootz ${loadaddr} - ${fdt_addr_r}; " \ | |
9b75bad0 SL |
220 | "else " \ |
221 | "if test ${boot_fdt} = try; then " \ | |
4ac0c2bf | 222 | "bootz; " \ |
9b75bad0 SL |
223 | "else " \ |
224 | "echo WARN: Cannot load the DT; " \ | |
225 | "fi; " \ | |
226 | "fi; " \ | |
227 | "else " \ | |
4ac0c2bf | 228 | "bootz; " \ |
5b94ce2c | 229 | "fi;\0" \ |
71bcdafe | 230 | "spilock=sf probe && sf protect lock 0x3f0000 0x10000;"\ |
9b75bad0 SL |
231 | |
232 | #define CONFIG_BOOTCOMMAND \ | |
71bcdafe | 233 | "run spilock;" \ |
d7140351 | 234 | "run findfdt; " \ |
5b94ce2c OS |
235 | "mmc dev ${mmcdev};" \ |
236 | "if mmc rescan; then " \ | |
237 | "if run loadbootscript; then " \ | |
238 | "run bootscript; " \ | |
239 | "else " \ | |
240 | "if run loadimage; then " \ | |
241 | "run mmcboot; " \ | |
242 | "else run netboot; " \ | |
243 | "fi; " \ | |
244 | "fi; " \ | |
245 | "else run netboot; fi" | |
9b75bad0 | 246 | |
9b75bad0 SL |
247 | #define CONFIG_SYS_MEMTEST_START 0x10000000 |
248 | #define CONFIG_SYS_MEMTEST_END 0x10010000 | |
249 | #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 | |
250 | ||
9b75bad0 SL |
251 | /* Physical Memory Map */ |
252 | #define CONFIG_NR_DRAM_BANKS 1 | |
253 | #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR | |
254 | #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024) | |
255 | ||
256 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM | |
257 | #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR | |
258 | #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE | |
259 | ||
260 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
261 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
262 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
263 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
264 | ||
056845c2 | 265 | /* Environment organization */ |
d5de9108 | 266 | #if defined (CONFIG_ENV_IS_IN_MMC) |
9b75bad0 SL |
267 | #define CONFIG_ENV_OFFSET (6 * 64 * 1024) |
268 | #define CONFIG_SYS_MMC_ENV_DEV 0 | |
d5de9108 OS |
269 | #endif |
270 | ||
271 | #define CONFIG_ENV_SIZE (8 * 1024) | |
272 | ||
273 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
274 | #if defined(CONFIG_ENV_IS_IN_SPI_FLASH) | |
275 | #define CONFIG_ENV_OFFSET (768 * 1024) | |
276 | #define CONFIG_ENV_SECT_SIZE (64 * 1024) | |
277 | #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS | |
278 | #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS | |
279 | #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE | |
280 | #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED | |
281 | #endif | |
9b75bad0 | 282 | |
9b75bad0 | 283 | #endif /* __CONFIG_CGTQMX6EVAL_H */ |