[people/ms/u-boot.git] / include / configs / cm-bf527.h

/*
 * U-Boot - Configuration file for CM-BF527 board
 */

#ifndef __CONFIG_CM_BF527_H__
#define __CONFIG_CM_BF527_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf527-0.0
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4

/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_120 | CLKBUFOE | FREQ_1000)

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	9
#define CONFIG_MEM_SIZE		32

#define CONFIG_EBIU_SDRRC_VAL	0x3f8
#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd

#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)

/*
 * NAND Settings
 * (can't be used sametime as ethernet)
 */
/* #define CONFIG_BFIN_NFC */
#ifdef CONFIG_BFIN_NFC
#define CONFIG_BFIN_NFC_CTL_VAL	0x0033
#define CONFIG_SYS_NAND_BASE		0 /* not actually used */
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_CMD_NAND
#endif

/*
 * Network Settings
 */
#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
    !defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_RMII
#define CONFIG_NETCONSOLE	1
#endif
#define CONFIG_HOSTNAME		cm-bf527

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT 	67

/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		0x20008000
#define CONFIG_ENV_OFFSET	0x8000
#define CONFIG_ENV_SIZE		0x8000
#define CONFIG_ENV_SECT_SIZE	0x8000
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * Misc Settings
 */
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BOOTCOMMAND	"run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
	"flashboot=flread 20040000 1000000 300000;" \
	"bootm 0x1000000\0"

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
59e4be94	1	/*
a187559e	2	* U-Boot - Configuration file for CM-BF527 board
59e4be94 MF	3	*/
	4
	5	#ifndef __CONFIG_CM_BF527_H__
	6	#define __CONFIG_CM_BF527_H__
	7
f348ab85	8	#include <asm/config-pre.h>
59e4be94	9
59e4be94 MF	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf527-0.0
59e4be94 MF	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_PARA
59e4be94 MF	15
59e4be94 MF	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 25000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 21
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 4
	38
fd04a05b HK	39	/* Decrease core voltage */
	40	#define CONFIG_VR_CTL_VAL (VLEV_120 \| CLKBUFOE \| FREQ_1000)
	41
59e4be94 MF	42	/*
	43	* Memory Settings
	44	*/
	45	#define CONFIG_MEM_ADD_WDTH 9
	46	#define CONFIG_MEM_SIZE 32
	47
	48	#define CONFIG_EBIU_SDRRC_VAL 0x3f8
	49	#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
	50
	51	#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
	52	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	53	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	54
	55	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	56	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	57
59e4be94 MF	58	/*
	59	* NAND Settings
	60	* (can't be used sametime as ethernet)
	61	*/
	62	/* #define CONFIG_BFIN_NFC */
	63	#ifdef CONFIG_BFIN_NFC
	64	#define CONFIG_BFIN_NFC_CTL_VAL 0x0033
	65	#define CONFIG_SYS_NAND_BASE 0 /* not actually used */
	66	#define CONFIG_SYS_MAX_NAND_DEVICE 1
59e4be94 MF	67	#define CONFIG_CMD_NAND
	68	#endif
	69
59e4be94 MF	70	/*
	71	* Network Settings
	72	*/
	73	#if !defined(__ADSPBF522__) && !defined(__ADSPBF523__) && \
	74	!defined(__ADSPBF524__) && !defined(__ADSPBF525__) && !defined(CONFIG_BFIN_NFC)
	75	#define ADI_CMDS_NETWORK 1
	76	#define CONFIG_BFIN_MAC
	77	#define CONFIG_RMII
	78	#define CONFIG_NETCONSOLE 1
59e4be94 MF	79	#endif
59e4be94 MF	80	#define CONFIG_HOSTNAME cm-bf527
59e4be94 MF	81
	82	/*
	83	* Flash Settings
	84	*/
	85	#define CONFIG_FLASH_CFI_DRIVER
	86	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	87	#define CONFIG_SYS_FLASH_BASE 0x20000000
	88	#define CONFIG_SYS_FLASH_CFI
	89	#define CONFIG_SYS_FLASH_PROTECTION
	90	#define CONFIG_SYS_MAX_FLASH_BANKS 1
c2fbcb6a	91	#define CONFIG_SYS_MAX_FLASH_SECT 67
59e4be94	92
59e4be94 MF	93	/*
	94	* Env Storage Settings
	95	*/
	96	#define CONFIG_ENV_IS_IN_FLASH 1
	97	#define CONFIG_ENV_ADDR 0x20008000
	98	#define CONFIG_ENV_OFFSET 0x8000
	99	#define CONFIG_ENV_SIZE 0x8000
fd04a05b	100	#define CONFIG_ENV_SECT_SIZE 0x8000
76d82187	101	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
59e4be94	102
59e4be94 MF	103	/*
	104	* I2C Settings
	105	*/
c469703b	106	#define CONFIG_SYS_I2C
fea9b69a	107	#define CONFIG_SYS_I2C_ADI
59e4be94	108
59e4be94 MF	109	/*
	110	* Misc Settings
	111	*/
59e4be94 MF	112	#define CONFIG_MISC_INIT_R
	113	#define CONFIG_RTC_BFIN
	114	#define CONFIG_UART_CONSOLE 0
fd04a05b HK	115	#define CONFIG_BOOTCOMMAND "run flashboot"
	116	#define FLASHBOOT_ENV_SETTINGS \
	117	"flashboot=flread 20040000 1000000 300000;" \
	118	"bootm 0x1000000\0"
59e4be94 MF	119
	120	/*
	121	* Pull in common ADI header for remaining command/environment setup
	122	*/
	123	#include <configs/bfin_adi_common.h>
	124
59e4be94	125	#endif