[people/ms/u-boot.git] / include / configs / cm-bf537e.h

/*
 * U-boot - Configuration file for CM-BF537E board
 */

#ifndef __CONFIG_CM_BF537E_H__
#define __CONFIG_CM_BF537E_H__

#include <asm/config-pre.h>


/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS


/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			21
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			4

/* Decrease core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_115 | CLKBUFOE | GAIN_20 | FREQ_1000)


/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	9
#define CONFIG_MEM_SIZE		32

#define CONFIG_EBIU_SDRRC_VAL	0x3f8
#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd

#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)


/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_BFIN_MAC
#define CONFIG_NETCONSOLE	1
#define CONFIG_NET_MULTI	1
#endif
#define CONFIG_HOSTNAME		cm-bf537e
/* Uncomment next line to use fixed MAC address */
/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */


/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	35


/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	0x4000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#else
#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/libblackfin.o (.text*); \
	arch/blackfin/cpu/libblackfin.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif


/*
 * I2C Settings
 */
#define CONFIG_BFIN_TWI_I2C	1
#define CONFIG_HARD_I2C		1


/*
 * Misc Settings
 */
#define CONFIG_BAUDRATE		115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BOOTCOMMAND	"run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
	"flashboot=flread 20040000 1000000 300000;" \
	"bootm 0x1000000\0"


/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
8a9bab08 MF	1	/*
	2	* U-boot - Configuration file for CM-BF537E board
	3	*/
	4
	5	#ifndef __CONFIG_CM_BF537E_H__
	6	#define __CONFIG_CM_BF537E_H__
	7
f348ab85	8	#include <asm/config-pre.h>
8a9bab08 MF	9
	10
	11	/*
	12	* Processor Settings
	13	*/
fbcf8e8c	14	#define CONFIG_BFIN_CPU bf537-0.2
8a9bab08 MF	15	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
	16
	17
	18	/*
	19	* Clock Settings
	20	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	21	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	22	*/
	23	/* CONFIG_CLKIN_HZ is any value in Hz */
	24	#define CONFIG_CLKIN_HZ 25000000
	25	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	26	/* 1 = CLKIN / 2 */
	27	#define CONFIG_CLKIN_HALF 0
	28	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	29	/* 1 = bypass PLL */
	30	#define CONFIG_PLL_BYPASS 0
	31	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	32	/* Values can range from 0-63 (where 0 means 64) */
	33	#define CONFIG_VCO_MULT 21
	34	/* CCLK_DIV controls the core clock divider */
	35	/* Values can be 1, 2, 4, or 8 ONLY */
	36	#define CONFIG_CCLK_DIV 1
	37	/* SCLK_DIV controls the system clock divider */
	38	/* Values can range from 1-15 */
	39	#define CONFIG_SCLK_DIV 4
	40
fd04a05b HK	41	/* Decrease core voltage */
	42	#define CONFIG_VR_CTL_VAL (VLEV_115 \| CLKBUFOE \| GAIN_20 \| FREQ_1000)
	43
8a9bab08 MF	44
	45	/*
	46	* Memory Settings
	47	*/
	48	#define CONFIG_MEM_ADD_WDTH 9
	49	#define CONFIG_MEM_SIZE 32
	50
	51	#define CONFIG_EBIU_SDRRC_VAL 0x3f8
	52	#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
	53
	54	#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
	55	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	56	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	57
	58	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	59	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
	60
	61
	62	/*
	63	* Network Settings
	64	*/
	65	#ifndef __ADSPBF534__
	66	#define ADI_CMDS_NETWORK 1
	67	#define CONFIG_BFIN_MAC
	68	#define CONFIG_NETCONSOLE 1
	69	#define CONFIG_NET_MULTI 1
	70	#endif
	71	#define CONFIG_HOSTNAME cm-bf537e
	72	/* Uncomment next line to use fixed MAC address */
	73	/* #define CONFIG_ETHADDR 02:80:ad:20:31:e8 */
	74
	75
	76	/*
	77	* Flash Settings
	78	*/
	79	#define CONFIG_FLASH_CFI_DRIVER
	80	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	81	#define CONFIG_SYS_FLASH_BASE 0x20000000
	82	#define CONFIG_SYS_FLASH_CFI
	83	#define CONFIG_SYS_FLASH_PROTECTION
	84	#define CONFIG_SYS_MAX_FLASH_BANKS 1
c2fbcb6a	85	#define CONFIG_SYS_MAX_FLASH_SECT 35
8a9bab08 MF	86
	87
	88	/*
	89	* Env Storage Settings
	90	*/
	91	#define CONFIG_ENV_IS_IN_FLASH 1
	92	#define CONFIG_ENV_OFFSET 0x4000
	93	#define CONFIG_ENV_SIZE 0x2000
	94	#define CONFIG_ENV_SECT_SIZE 0x20000
	95	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
	96	#define ENV_IS_EMBEDDED
	97	#else
76d82187	98	#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
8a9bab08	99	#endif
9ff67e5e MF	100	#ifdef ENV_IS_EMBEDDED
	101	/* WARNING - the following is hand-optimized to fit within
	102	* the sector before the environment sector. If it throws
	103	* an error during compilation remove an object here to get
	104	* it linked after the configuration sector.
	105	*/
	106	# define LDS_BOARD_TEXT \
c70e7ddb MF	107	arch/blackfin/lib/libblackfin.o (.text*); \
c70e7ddb MF	108	arch/blackfin/cpu/libblackfin.o (.text*); \
9ff67e5e	109	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	110	common/env_embedded.o (.text*);
9ff67e5e	111	#endif
8a9bab08 MF	112
	113
	114	/*
	115	* I2C Settings
	116	*/
	117	#define CONFIG_BFIN_TWI_I2C 1
	118	#define CONFIG_HARD_I2C 1
8a9bab08 MF	119
	120
	121	/*
	122	* Misc Settings
	123	*/
	124	#define CONFIG_BAUDRATE 115200
	125	#define CONFIG_MISC_INIT_R
	126	#define CONFIG_RTC_BFIN
	127	#define CONFIG_UART_CONSOLE 0
fd04a05b HK	128	#define CONFIG_BOOTCOMMAND "run flashboot"
	129	#define FLASHBOOT_ENV_SETTINGS \
	130	"flashboot=flread 20040000 1000000 300000;" \
	131	"bootm 0x1000000\0"
8a9bab08 MF	132
	133
	134	/*
	135	* Pull in common ADI header for remaining command/environment setup
	136	*/
	137	#include <configs/bfin_adi_common.h>
	138
8a9bab08	139	#endif