[people/ms/u-boot.git] / include / configs / cm-bf537u.h

/*
 * U-Boot - Configuration file for CM-BF537U board
 */

#ifndef __CONFIG_CM_BF537U_H__
#define __CONFIG_CM_BF537U_H__

#include <asm/config-pre.h>

/*
 * Processor Settings
 */
#define CONFIG_BFIN_CPU             bf537-0.2
#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS

/*
 * Clock Settings
 *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
 *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
 */
/* CONFIG_CLKIN_HZ is any value in Hz					*/
#define CONFIG_CLKIN_HZ			30000000
/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
/*                                                1 = CLKIN / 2		*/
#define CONFIG_CLKIN_HALF		0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
/*                                                1 = bypass PLL	*/
#define CONFIG_PLL_BYPASS		0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
/* Values can range from 0-63 (where 0 means 64)			*/
#define CONFIG_VCO_MULT			18
/* CCLK_DIV controls the core clock divider				*/
/* Values can be 1, 2, 4, or 8 ONLY					*/
#define CONFIG_CCLK_DIV			1
/* SCLK_DIV controls the system clock divider				*/
/* Values can range from 1-15						*/
#define CONFIG_SCLK_DIV			5
/* Core voltage */
#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)

/*
 * Memory Settings
 */
#define CONFIG_MEM_ADD_WDTH	9
#define CONFIG_MEM_SIZE		32

#define CONFIG_EBIU_SDRRC_VAL	0x3f8
#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd

#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)

#define CONFIG_SYS_MONITOR_LEN	(768 * 1024)
#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)

/*
 * Network Settings
 */
#ifndef __ADSPBF534__
#define ADI_CMDS_NETWORK	1
#define CONFIG_SMC911X		1
#define CONFIG_SMC911X_BASE	0x20308000
#define CONFIG_SMC911X_16_BIT
#define CONFIG_NETCONSOLE	1
#endif
#define CONFIG_HOSTNAME		cm-bf537u

/*
 * Flash Settings
 */
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
#define CONFIG_SYS_FLASH_BASE		0x20000000
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_PROTECTION
#define CONFIG_SYS_MAX_FLASH_BANKS	1
#define CONFIG_SYS_MAX_FLASH_SECT	35

/*
 * SPI Settings
 */
#define CONFIG_BFIN_SPI
#define CONFIG_ENV_SPI_MAX_HZ	30000000

/*
 * Env Storage Settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_OFFSET	0x8000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
#define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
#define CONFIG_ENV_SECT_SIZE	0x8000
#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
#define ENV_IS_EMBEDDED
#endif
#ifdef ENV_IS_EMBEDDED
/* WARNING - the following is hand-optimized to fit within
 * the sector before the environment sector. If it throws
 * an error during compilation remove an object here to get
 * it linked after the configuration sector.
 */
# define LDS_BOARD_TEXT \
	arch/blackfin/lib/built-in.o (.text*); \
	arch/blackfin/cpu/built-in.o (.text*); \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o (.text*);
#endif

/*
 * I2C Settings
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_ADI

/*
 * SPI_MMC Settings
 */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC_SPI

/*
 * Misc Settings
 */
#define CONFIG_BAUDRATE		115200
#define CONFIG_MISC_INIT_R
#define CONFIG_RTC_BFIN
#define CONFIG_UART_CONSOLE	0
#define CONFIG_BOOTCOMMAND	"run flashboot"
#define FLASHBOOT_ENV_SETTINGS \
	"flashboot=flread 20040000 1000000 300000;" \
	"bootm 0x1000000\0"
#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))

/*
 * Pull in common ADI header for remaining command/environment setup
 */
#include <configs/bfin_adi_common.h>

#endif
Commit	Line	Data
4640c2b8	1	/*
a187559e	2	* U-Boot - Configuration file for CM-BF537U board
4640c2b8 HK	3	*/
	4
	5	#ifndef __CONFIG_CM_BF537U_H__
	6	#define __CONFIG_CM_BF537U_H__
	7
	8	#include <asm/config-pre.h>
	9
4640c2b8 HK	10	/*
	11	* Processor Settings
	12	*/
fbcf8e8c	13	#define CONFIG_BFIN_CPU bf537-0.2
4640c2b8 HK	14	#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
4640c2b8 HK	15
4640c2b8 HK	16	/*
	17	* Clock Settings
	18	* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
	19	* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
	20	*/
	21	/* CONFIG_CLKIN_HZ is any value in Hz */
	22	#define CONFIG_CLKIN_HZ 30000000
	23	/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
	24	/* 1 = CLKIN / 2 */
	25	#define CONFIG_CLKIN_HALF 0
	26	/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
	27	/* 1 = bypass PLL */
	28	#define CONFIG_PLL_BYPASS 0
	29	/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
	30	/* Values can range from 0-63 (where 0 means 64) */
	31	#define CONFIG_VCO_MULT 18
	32	/* CCLK_DIV controls the core clock divider */
	33	/* Values can be 1, 2, 4, or 8 ONLY */
	34	#define CONFIG_CCLK_DIV 1
	35	/* SCLK_DIV controls the system clock divider */
	36	/* Values can range from 1-15 */
	37	#define CONFIG_SCLK_DIV 5
	38	/* Core voltage */
	39	#define CONFIG_VR_CTL_VAL (VLEV_110 \| GAIN_20 \| FREQ_1000)
	40
4640c2b8 HK	41	/*
	42	* Memory Settings
	43	*/
	44	#define CONFIG_MEM_ADD_WDTH 9
	45	#define CONFIG_MEM_SIZE 32
	46
	47	#define CONFIG_EBIU_SDRRC_VAL 0x3f8
	48	#define CONFIG_EBIU_SDGCTL_VAL 0x9111cd
	49
	50	#define CONFIG_EBIU_AMGCTL_VAL (AMBEN_ALL)
	51	#define CONFIG_EBIU_AMBCTL0_VAL (B1WAT_7 \| B1RAT_11 \| B1HT_2 \| B1ST_3 \| B0WAT_7 \| B0RAT_11 \| B0HT_2 \| B0ST_3)
	52	#define CONFIG_EBIU_AMBCTL1_VAL (B3WAT_7 \| B3RAT_11 \| B3HT_2 \| B3ST_3 \| B2WAT_7 \| B2RAT_11 \| B2HT_2 \| B2ST_3)
	53
6e6b221c	54	#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
4640c2b8 HK	55	#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
4640c2b8 HK	56
4640c2b8 HK	57	/*
	58	* Network Settings
	59	*/
	60	#ifndef __ADSPBF534__
	61	#define ADI_CMDS_NETWORK 1
fff18bee HK	62	#define CONFIG_SMC911X 1
fff18bee HK	63	#define CONFIG_SMC911X_BASE 0x20308000
4640c2b8	64	#define CONFIG_SMC911X_16_BIT
fff18bee	65	#define CONFIG_NETCONSOLE 1
4640c2b8 HK	66	#endif
4640c2b8 HK	67	#define CONFIG_HOSTNAME cm-bf537u
4640c2b8 HK	68
	69	/*
	70	* Flash Settings
	71	*/
	72	#define CONFIG_FLASH_CFI_DRIVER
	73	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	74	#define CONFIG_SYS_FLASH_BASE 0x20000000
	75	#define CONFIG_SYS_FLASH_CFI
	76	#define CONFIG_SYS_FLASH_PROTECTION
	77	#define CONFIG_SYS_MAX_FLASH_BANKS 1
	78	#define CONFIG_SYS_MAX_FLASH_SECT 35
	79
c94101ae HK	80	/*
	81	* SPI Settings
	82	*/
	83	#define CONFIG_BFIN_SPI
	84	#define CONFIG_ENV_SPI_MAX_HZ 30000000
	85
4640c2b8 HK	86	/*
	87	* Env Storage Settings
	88	*/
	89	#define CONFIG_ENV_IS_IN_FLASH 1
ba5c1228 HK	90	#define CONFIG_ENV_OFFSET 0x8000
	91	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
	92	#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
	93	#define CONFIG_ENV_SECT_SIZE 0x8000
4640c2b8 HK	94	#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
4640c2b8 HK	95	#define ENV_IS_EMBEDDED
4640c2b8 HK	96	#endif
	97	#ifdef ENV_IS_EMBEDDED
	98	/* WARNING - the following is hand-optimized to fit within
	99	* the sector before the environment sector. If it throws
	100	* an error during compilation remove an object here to get
	101	* it linked after the configuration sector.
	102	*/
	103	# define LDS_BOARD_TEXT \
e2906a59 MY	104	arch/blackfin/lib/built-in.o (.text*); \
e2906a59 MY	105	arch/blackfin/cpu/built-in.o (.text*); \
4640c2b8	106	. = DEFINED(env_offset) ? env_offset : .; \
c70e7ddb	107	common/env_embedded.o (.text*);
4640c2b8 HK	108	#endif
4640c2b8 HK	109
4640c2b8 HK	110	/*
	111	* I2C Settings
	112	*/
c469703b	113	#define CONFIG_SYS_I2C
fea9b69a	114	#define CONFIG_SYS_I2C_ADI
4640c2b8	115
c94101ae HK	116	/*
	117	* SPI_MMC Settings
	118	*/
	119	#define CONFIG_MMC
	120	#define CONFIG_GENERIC_MMC
	121	#define CONFIG_MMC_SPI
	122
4640c2b8 HK	123	/*
	124	* Misc Settings
	125	*/
	126	#define CONFIG_BAUDRATE 115200
	127	#define CONFIG_MISC_INIT_R
	128	#define CONFIG_RTC_BFIN
	129	#define CONFIG_UART_CONSOLE 0
fd04a05b HK	130	#define CONFIG_BOOTCOMMAND "run flashboot"
fd04a05b HK	131	#define FLASHBOOT_ENV_SETTINGS \
ba5c1228	132	"flashboot=flread 20040000 1000000 300000;" \
fd04a05b	133	"bootm 0x1000000\0"
6e6b221c	134	#define CONFIG_BOARD_SIZE_LIMIT $$((384 * 1024))
4640c2b8 HK	135
	136	/*
	137	* Pull in common ADI header for remaining command/environment setup
	138	*/
	139	#include <configs/bfin_adi_common.h>
	140
4640c2b8	141	#endif