[people/ms/u-boot.git] / include / configs / cm5200.h

/*
 * (C) Copyright 2003-2007
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_MPC5200		1	/* This is an MPC5200 CPU */
#define CONFIG_CM5200		1	/* ... on CM5200 platform */

#define	CONFIG_SYS_TEXT_BASE	0xfc000000

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/*
 * Supported commands
 */
#define CONFIG_CMD_BSP
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DIAG
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO

/*
 * Serial console configuration
 */
#define CONFIG_PSC_CONSOLE	1	/* console is on PSC1 */
#define CONFIG_BAUDRATE		57600	/* ... at 57600 bps */
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

/*
 * Ethernet configuration
 */
#define CONFIG_MPC5xxx_FEC	1
#define CONFIG_MPC5xxx_FEC_MII100
#define CONFIG_PHY_ADDR		0x00
#define CONFIG_ENV_OVERWRITE	1	/* allow overwriting of ethaddr */
/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
#define CONFIG_MISC_INIT_R	1
#define CONFIG_MAC_OFFSET	0x35	/* MAC address offset in I2C EEPROM */

/*
 * POST support
 */
#define CONFIG_POST		(CONFIG_SYS_POST_MEMORY | CONFIG_SYS_POST_CPU | CONFIG_SYS_POST_I2C)
#define MPC5XXX_SRAM_POST_SIZE	(MPC5XXX_SRAM_SIZE - 4)
/* List of I2C addresses to be verified by POST */
#define CONFIG_SYS_POST_I2C_ADDRS	{CONFIG_SYS_I2C_SLAVE,	\
					 CONFIG_SYS_I2C_IO,	\
					 CONFIG_SYS_I2C_EEPROM}

/* display image timestamps */
#define CONFIG_TIMESTAMP	1

/*
 * Autobooting
 */
#define CONFIG_PREBOOT	"echo;" \
	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
	"echo"
#undef CONFIG_BOOTARGS

/*
 * Default environment settings
 */
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"netmask=255.255.0.0\0"						\
	"ipaddr=192.168.160.33\0"					\
	"serverip=192.168.1.1\0"					\
	"gatewayip=192.168.1.1\0"					\
	"console=ttyPSC0\0"						\
	"u-boot_addr=100000\0"						\
	"kernel_addr=200000\0"						\
	"kernel_addr_flash=fc0c0000\0"					\
	"fdt_addr=400000\0"						\
	"fdt_addr_flash=fc0a0000\0"					\
	"ramdisk_addr=500000\0"						\
	"rootpath=/opt/eldk-4.1/ppc_6xx\0"				\
	"u-boot=/tftpboot/cm5200/u-boot.bin\0"				\
	"bootfile_fdt=/tftpboot/cm5200/uImage\0"			\
	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0"			\
	"load=tftp ${u-boot_addr} ${u-boot}\0"				\
	"update=prot off fc000000 +${filesize}; "			\
		"era fc000000 +${filesize}; "				\
		"cp.b ${u-boot_addr} fc000000 ${filesize}; "		\
		"prot on fc000000 +${filesize}\0"			\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0"		\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0"		\
	"addcons=setenv bootargs ${bootargs} "				\
		"console=${console},${baudrate}\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
		"${netmask}:${hostname}:${netdev}:off panic=1\0"	\
	"flash_flash=run flashargs addinit addip addcons;"		\
		"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0"	\
	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; "		\
		"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip "	\
		"addcons; bootm ${kernel_addr} - ${fdt_addr}\0"		\
	""
#define CONFIG_BOOTCOMMAND	"run flash_flash"

/*
 * Low level configuration
 */

/*
 * Clock configuration
 */
#define CONFIG_SYS_MPC5XXX_CLKIN	33000000	/* SYS_XTAL_IN = 33MHz */
#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK	1	/* IPB = 133MHz */

/*
 * Memory map
 */
#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_DEFAULT_MBAR	0x80000000

#define CONFIG_SYS_LOWBOOT		1

/* Use ON-Chip SRAM until RAM will be available */
#define CONFIG_SYS_INIT_RAM_ADDR	MPC5XXX_SRAM
#ifdef CONFIG_POST
/* preserve space for the post_word at end of on-chip SRAM */
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_POST_SIZE
#else
#define CONFIG_SYS_INIT_RAM_SIZE	MPC5XXX_SRAM_SIZE
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_BOARD_TYPES	1	/* we use board_type */

#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* 384 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)	/* 256 kB for malloc() */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* initial mem map for Linux */

/*
 * Flash configuration
 */
#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_BASE		0xfc000000
/* we need these despite using CFI */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max num of flash banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sectors on one chip */
#define CONFIG_SYS_FLASH_SIZE		0x02000000 /* 32 MiB */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT		1
#undef CONFIG_SYS_LOWBOOT
#endif

/*
 * Chip selects configuration
 */
/* Boot Chipselect */
#define CONFIG_SYS_BOOTCS_START	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_BOOTCS_SIZE		CONFIG_SYS_FLASH_SIZE
#define CONFIG_SYS_BOOTCS_CFG		0x00087D31	/* for pci_clk = 33 MHz */
/* use board_early_init_r to enable flash write in CS_BOOT */
#define CONFIG_BOARD_EARLY_INIT_R

/* Flash memory addressing */
#define CONFIG_SYS_CS0_START		CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_CS0_SIZE		CONFIG_SYS_FLASH_SIZE

/* No burst, dead cycle = 1 for CS0 (Flash) */
#define CONFIG_SYS_CS_BURST		0x00000000
#define CONFIG_SYS_CS_DEADCYCLE	0x00000001

/*
 * SDRAM configuration
 * settings for k4s561632E-xx75, assuming XLB = 132 MHz
 */
#define SDRAM_MODE	0x00CD0000	/* CASL 3, burst length 8 */
#define SDRAM_CONTROL	0x514F0000
#define SDRAM_CONFIG1	0xE2333900
#define SDRAM_CONFIG2	0x8EE70000

/*
 * MTD configuration
 */
#define CONFIG_CMD_MTDPARTS	1
#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
#define CONFIG_FLASH_CFI_MTD
#define MTDIDS_DEFAULT		"nor0=cm5200-0"
#define MTDPARTS_DEFAULT	"mtdparts=cm5200-0:"			\
					"384k(uboot),128k(env),"	\
					"128k(redund_env),128k(dtb),"	\
					"2m(kernel),27904k(rootfs),"	\
					"-(config)"

/*
 * I2C configuration
 */
#define CONFIG_HARD_I2C		1	/* I2C with hardware support */
#define CONFIG_SYS_I2C_MODULE		2	/* Select I2C module #2 */
#define CONFIG_SYS_I2C_SPEED		40000	/* 40 kHz */
#define CONFIG_SYS_I2C_SLAVE		0x0
#define CONFIG_SYS_I2C_IO		0x38	/* PCA9554AD I2C I/O port address */
#define CONFIG_SYS_I2C_EEPROM		0x53	/* I2C EEPROM device address */

/*
 * RTC configuration
 */
#define CONFIG_RTC_MPC5200	1	/* use internal MPC5200 RTC */

/*
 * USB configuration
 */
#define CONFIG_USB_OHCI		1
#define CONFIG_USB_CLOCK	0x0001BBBB
#define CONFIG_USB_CONFIG	0x00001000
/* Partitions (for USB) */

/*
 * Invoke our last_stage_init function - needed by fwupdate
 */
#define CONFIG_LAST_STAGE_INIT	1

/*
 * Environment settings
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SIZE		0x10000
#define CONFIG_ENV_SECT_SIZE	0x20000
#define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
/* Configuration of redundant environment */
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*
 * Pin multiplexing configuration
 */

/*
 * CS1/GPIO_WKUP_6: GPIO (default)
 * ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
 * IRDA/PSC6: UART
 * Ether: Ethernet 100Mbit with MD
 * PCI_DIS: PCI controller disabled
 * USB: USB
 * PSC3: SPI with UART3
 * PSC2: UART
 * PSC1: UART
 */
#define CONFIG_SYS_GPS_PORT_CONFIG	0x10559C44

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		1	/* undef to save memory */
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_ALT_MEMTEST		1
#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x03f00000	/* 1 .. 63 MiB in SDRAM */

#define CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address */

/*
 * Various low-level settings
 */
#define CONFIG_SYS_HID0_INIT		HID0_ICE | HID0_ICFI
#define CONFIG_SYS_HID0_FINAL		HID0_ICE

#define CONFIG_SYS_XLB_PIPELINING	1	/* enable transaction pipeling */

/*
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	32	/* For MPC5xxx CPUs */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Flat Device Tree support
 */
#define OF_CPU			"PowerPC,5200@0"
#define OF_SOC			"soc5200@f0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc5200@f0000000/serial@2000"

#endif /* __CONFIG_H */
Commit	Line	Data
fa1df308 BS	1	/*
	2	* (C) Copyright 2003-2007
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
fa1df308 BS	6	*/
	7
	8	#ifndef __CONFIG_H
	9	#define __CONFIG_H
	10
	11	/*
	12	* High Level Configuration Options
	13	*/
b2a6dfe4	14	#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
86b116b1	15	#define CONFIG_CM5200 1 /* ... on CM5200 platform */
fa1df308	16
2ae18241 WD	17	#define CONFIG_SYS_TEXT_BASE 0xfc000000
2ae18241 WD	18
31d82672 BB	19	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	20
fa1df308 BS	21	/*
	22	* Supported commands
	23	*/
afaac86f WD	24	#define CONFIG_CMD_BSP
afaac86f WD	25	#define CONFIG_CMD_DATE
afaac86f	26	#define CONFIG_CMD_DIAG
afaac86f	27	#define CONFIG_CMD_JFFS2
afaac86f	28	#define CONFIG_CMD_REGINFO
fa1df308 BS	29
	30	/*
	31	* Serial console configuration
	32	*/
	33	#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
	34	#define CONFIG_BAUDRATE 57600 /* ... at 57600 bps */
6d0f6bcf	35	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
fa1df308	36
fa1df308 BS	37	/*
	38	* Ethernet configuration
	39	*/
	40	#define CONFIG_MPC5xxx_FEC 1
86321fc1	41	#define CONFIG_MPC5xxx_FEC_MII100
fa1df308 BS	42	#define CONFIG_PHY_ADDR 0x00
fa1df308 BS	43	#define CONFIG_ENV_OVERWRITE 1 /* allow overwriting of ethaddr */
6d0f6bcf	44	/* use misc_init_r() to read ethaddr from I2C EEPROM (see CONFIG_SYS_I2C_EEPROM) */
fa1df308 BS	45	#define CONFIG_MISC_INIT_R 1
	46	#define CONFIG_MAC_OFFSET 0x35 /* MAC address offset in I2C EEPROM */
	47
fa1df308 BS	48	/*
	49	* POST support
	50	*/
6d0f6bcf	51	#define CONFIG_POST (CONFIG_SYS_POST_MEMORY \| CONFIG_SYS_POST_CPU \| CONFIG_SYS_POST_I2C)
fa1df308 BS	52	#define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
fa1df308 BS	53	/* List of I2C addresses to be verified by POST */
60aaaa07 PT	54	#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_SLAVE, \
	55	CONFIG_SYS_I2C_IO, \
	56	CONFIG_SYS_I2C_EEPROM}
fa1df308	57
fa1df308 BS	58	/* display image timestamps */
	59	#define CONFIG_TIMESTAMP 1
	60
fa1df308 BS	61	/*
	62	* Autobooting
	63	*/
fa1df308 BS	64	#define CONFIG_PREBOOT "echo;" \
	65	"echo Type \"run net_nfs_fdt\" to mount root filesystem over NFS;" \
	66	"echo"
	67	#undef CONFIG_BOOTARGS
	68
	69	/*
	70	* Default environment settings
	71	*/
	72	#define CONFIG_EXTRA_ENV_SETTINGS \
	73	"netdev=eth0\0" \
fa1df308 BS	74	"netmask=255.255.0.0\0" \
	75	"ipaddr=192.168.160.33\0" \
	76	"serverip=192.168.1.1\0" \
	77	"gatewayip=192.168.1.1\0" \
	78	"console=ttyPSC0\0" \
	79	"u-boot_addr=100000\0" \
	80	"kernel_addr=200000\0" \
	81	"kernel_addr_flash=fc0c0000\0" \
	82	"fdt_addr=400000\0" \
	83	"fdt_addr_flash=fc0a0000\0" \
	84	"ramdisk_addr=500000\0" \
	85	"rootpath=/opt/eldk-4.1/ppc_6xx\0" \
86b116b1 BS	86	"u-boot=/tftpboot/cm5200/u-boot.bin\0" \
	87	"bootfile_fdt=/tftpboot/cm5200/uImage\0" \
	88	"fdt_file=/tftpboot/cm5200/cm5200.dtb\0" \
fa1df308	89	"load=tftp ${u-boot_addr} ${u-boot}\0" \
86b116b1 BS	90	"update=prot off fc000000 +${filesize}; " \
86b116b1 BS	91	"era fc000000 +${filesize}; " \
fa1df308	92	"cp.b ${u-boot_addr} fc000000 ${filesize}; " \
86b116b1	93	"prot on fc000000 +${filesize}\0" \
fa1df308 BS	94	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	95	"nfsroot=${serverip}:${rootpath}\0" \
	96	"flashargs=setenv bootargs root=/dev/mtdblock5 rw\0" \
	97	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	98	"addinit=setenv bootargs ${bootargs} init=/linuxrc\0" \
	99	"addcons=setenv bootargs ${bootargs} " \
	100	"console=${console},${baudrate}\0" \
	101	"addip=setenv bootargs ${bootargs} " \
	102	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	103	"${netmask}:${hostname}:${netdev}:off panic=1\0" \
	104	"flash_flash=run flashargs addinit addip addcons;" \
	105	"bootm ${kernel_addr_flash} - ${fdt_addr_flash}\0" \
	106	"net_nfs_fdt=tftp ${kernel_addr} ${bootfile_fdt}; " \
	107	"tftp ${fdt_addr} ${fdt_file}; run nfsargs addip " \
	108	"addcons; bootm ${kernel_addr} - ${fdt_addr}\0" \
	109	""
	110	#define CONFIG_BOOTCOMMAND "run flash_flash"
	111
fa1df308 BS	112	/*
	113	* Low level configuration
	114	*/
	115
fa1df308 BS	116	/*
	117	* Clock configuration
	118	*/
6d0f6bcf JCPV	119	#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* SYS_XTAL_IN = 33MHz */
6d0f6bcf JCPV	120	#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK 1 /* IPB = 133MHz */
fa1df308	121
fa1df308 BS	122	/*
	123	* Memory map
	124	*/
6d0f6bcf JCPV	125	#define CONFIG_SYS_MBAR 0xF0000000
	126	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	127	#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
fa1df308	128
6d0f6bcf	129	#define CONFIG_SYS_LOWBOOT 1
fa1df308 BS	130
fa1df308 BS	131	/* Use ON-Chip SRAM until RAM will be available */
6d0f6bcf	132	#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
fa1df308 BS	133	#ifdef CONFIG_POST
fa1df308 BS	134	/* preserve space for the post_word at end of on-chip SRAM */
553f0982	135	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_POST_SIZE
fa1df308	136	#else
553f0982	137	#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
fa1df308 BS	138	#endif
fa1df308 BS	139
25ddd1fb	140	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
86b116b1 BS	141	#define CONFIG_BOARD_TYPES 1 /* we use board_type */
86b116b1 BS	142
6d0f6bcf	143	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
fa1df308	144
14d0a02a	145	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	146	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* 384 kB for Monitor */
	147	#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* 256 kB for malloc() */
	148	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* initial mem map for Linux */
fa1df308	149
86b116b1 BS	150	/*
	151	* Flash configuration
	152	*/
6d0f6bcf	153	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	154	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	155	#define CONFIG_SYS_FLASH_BASE 0xfc000000
86b116b1	156	/* we need these despite using CFI */
6d0f6bcf JCPV	157	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
	158	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sectors on one chip */
	159	#define CONFIG_SYS_FLASH_SIZE 0x02000000 /* 32 MiB */
86b116b1	160
6d0f6bcf JCPV	161	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
	162	#define CONFIG_SYS_RAMBOOT 1
	163	#undef CONFIG_SYS_LOWBOOT
fa1df308 BS	164	#endif
fa1df308 BS	165
fa1df308 BS	166	/*
	167	* Chip selects configuration
	168	*/
	169	/* Boot Chipselect */
6d0f6bcf JCPV	170	#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
	171	#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
	172	#define CONFIG_SYS_BOOTCS_CFG 0x00087D31 /* for pci_clk = 33 MHz */
fa1df308 BS	173	/* use board_early_init_r to enable flash write in CS_BOOT */
	174	#define CONFIG_BOARD_EARLY_INIT_R
	175
	176	/* Flash memory addressing */
6d0f6bcf JCPV	177	#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	178	#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
fa1df308 BS	179
fa1df308 BS	180	/* No burst, dead cycle = 1 for CS0 (Flash) */
6d0f6bcf JCPV	181	#define CONFIG_SYS_CS_BURST 0x00000000
6d0f6bcf JCPV	182	#define CONFIG_SYS_CS_DEADCYCLE 0x00000001
fa1df308	183
fa1df308 BS	184	/*
	185	* SDRAM configuration
	186	* settings for k4s561632E-xx75, assuming XLB = 132 MHz
	187	*/
	188	#define SDRAM_MODE 0x00CD0000 /* CASL 3, burst length 8 */
	189	#define SDRAM_CONTROL 0x514F0000
	190	#define SDRAM_CONFIG1 0xE2333900
	191	#define SDRAM_CONFIG2 0x8EE70000
	192
fa1df308 BS	193	/*
	194	* MTD configuration
	195	*/
68d7d651	196	#define CONFIG_CMD_MTDPARTS 1
942556a9 SR	197	#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
942556a9 SR	198	#define CONFIG_FLASH_CFI_MTD
86b116b1 BS	199	#define MTDIDS_DEFAULT "nor0=cm5200-0"
86b116b1 BS	200	#define MTDPARTS_DEFAULT "mtdparts=cm5200-0:" \
fa1df308 BS	201	"384k(uboot),128k(env)," \
	202	"128k(redund_env),128k(dtb)," \
	203	"2m(kernel),27904k(rootfs)," \
	204	"-(config)"
	205
fa1df308 BS	206	/*
	207	* I2C configuration
	208	*/
	209	#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
6d0f6bcf JCPV	210	#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 */
	211	#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz */
	212	#define CONFIG_SYS_I2C_SLAVE 0x0
	213	#define CONFIG_SYS_I2C_IO 0x38 /* PCA9554AD I2C I/O port address */
	214	#define CONFIG_SYS_I2C_EEPROM 0x53 /* I2C EEPROM device address */
fa1df308	215
fa1df308 BS	216	/*
	217	* RTC configuration
	218	*/
	219	#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */
	220
fa1df308 BS	221	/*
	222	* USB configuration
	223	*/
	224	#define CONFIG_USB_OHCI 1
fa1df308 BS	225	#define CONFIG_USB_CLOCK 0x0001BBBB
	226	#define CONFIG_USB_CONFIG 0x00001000
	227	/* Partitions (for USB) */
fa1df308 BS	228
	229	/*
	230	* Invoke our last_stage_init function - needed by fwupdate
	231	*/
	232	#define CONFIG_LAST_STAGE_INIT 1
	233
	234	/*
	235	* Environment settings
	236	*/
5a1aceb0	237	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	238	#define CONFIG_ENV_SIZE 0x10000
0e8d1586 JCPV	239	#define CONFIG_ENV_SECT_SIZE 0x20000
6d0f6bcf	240	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
fa1df308	241	/* Configuration of redundant environment */
0e8d1586 JCPV	242	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	243	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
fa1df308	244
fa1df308 BS	245	/*
	246	* Pin multiplexing configuration
	247	*/
	248
	249	/*
	250	* CS1/GPIO_WKUP_6: GPIO (default)
	251	* ALTs: CAN1 on I2C1, CAN2 on TIMER0/1
	252	* IRDA/PSC6: UART
	253	* Ether: Ethernet 100Mbit with MD
	254	* PCI_DIS: PCI controller disabled
	255	* USB: USB
	256	* PSC3: SPI with UART3
	257	* PSC2: UART
	258	* PSC1: UART
	259	*/
6d0f6bcf	260	#define CONFIG_SYS_GPS_PORT_CONFIG 0x10559C44
fa1df308	261
fa1df308 BS	262	/*
	263	* Miscellaneous configurable options
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
6d0f6bcf JCPV	266	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	267	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	268	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	269	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
fa1df308	270
6d0f6bcf JCPV	271	#define CONFIG_SYS_ALT_MEMTEST 1
	272	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
	273	#define CONFIG_SYS_MEMTEST_END 0x03f00000 /* 1 .. 63 MiB in SDRAM */
fa1df308	274
6d0f6bcf	275	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
fa1df308	276
fa1df308 BS	277	/*
	278	* Various low-level settings
	279	*/
6d0f6bcf JCPV	280	#define CONFIG_SYS_HID0_INIT HID0_ICE \| HID0_ICFI
6d0f6bcf JCPV	281	#define CONFIG_SYS_HID0_FINAL HID0_ICE
fa1df308	282
6d0f6bcf	283	#define CONFIG_SYS_XLB_PIPELINING 1 /* enable transaction pipeling */
fa1df308	284
fa1df308 BS	285	/*
	286	* Cache Configuration
	287	*/
6d0f6bcf	288	#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
afaac86f	289	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	290	#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
fa1df308 BS	291	#endif
fa1df308 BS	292
fa1df308 BS	293	/*
	294	* Flat Device Tree support
	295	*/
fa1df308 BS	296	#define OF_CPU "PowerPC,5200@0"
	297	#define OF_SOC "soc5200@f0000000"
	298	#define OF_TBCLK (bd->bi_busfreq / 4)
	299	#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
	300
	301	#endif /* __CONFIG_H */