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54e7445d IL |
1 | /* |
2 | * Config file for Compulab CM-T335 board | |
3 | * | |
4 | * Copyright (C) 2013, Compulab Ltd - http://compulab.co.il/ | |
5 | * | |
6 | * Author: Ilya Ledvich <ilya@compulab.co.il> | |
7 | * | |
8 | * SPDX-License-Identifier: GPL-2.0+ | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_CM_T335_H | |
12 | #define __CONFIG_CM_T335_H | |
13 | ||
14 | #define CONFIG_CM_T335 | |
54e7445d IL |
15 | |
16 | #include <configs/ti_am335x_common.h> | |
17 | ||
54e7445d | 18 | #undef CONFIG_SPI |
54e7445d IL |
19 | #undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC |
20 | ||
21 | #undef CONFIG_MAX_RAM_BANK_SIZE | |
22 | #define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* 512MB */ | |
23 | ||
54e7445d IL |
24 | #define CONFIG_MACH_TYPE MACH_TYPE_CM_T335 |
25 | ||
26 | /* Clock Defines */ | |
27 | #define V_OSCK 25000000 /* Clock output from T2 */ | |
28 | #define V_SCLK (V_OSCK) | |
29 | ||
30 | #define CONFIG_ENV_SIZE (16 << 10) /* 16 KiB */ | |
31 | ||
32 | #ifndef CONFIG_SPL_BUILD | |
33 | #define MMCARGS \ | |
34 | "mmcdev=0\0" \ | |
35 | "mmcroot=/dev/mmcblk0p2 rw rootwait\0" \ | |
36 | "mmcrootfstype=ext4\0" \ | |
37 | "mmcargs=setenv bootargs console=${console} " \ | |
38 | "root=${mmcroot} " \ | |
39 | "rootfstype=${mmcrootfstype}\0" \ | |
40 | "mmcboot=echo Booting from mmc ...; " \ | |
41 | "run mmcargs; " \ | |
42 | "bootm ${loadaddr}\0" | |
43 | ||
44 | #define NANDARGS \ | |
43ede0bc TR |
45 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \ |
46 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \ | |
54e7445d IL |
47 | "nandroot=ubi0:rootfs rw\0" \ |
48 | "nandrootfstype=ubifs\0" \ | |
49 | "nandargs=setenv bootargs console=${console} " \ | |
50 | "root=${nandroot} " \ | |
51 | "rootfstype=${nandrootfstype} " \ | |
52 | "ubi.mtd=${rootfs_name}\0" \ | |
53 | "nandboot=echo Booting from nand ...; " \ | |
54 | "run nandargs; " \ | |
55 | "nboot ${loadaddr} nand0 900000; " \ | |
56 | "bootm ${loadaddr}\0" | |
57 | ||
54e7445d IL |
58 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
59 | "loadaddr=82000000\0" \ | |
60 | "console=ttyO0,115200n8\0" \ | |
61 | "rootfs_name=rootfs\0" \ | |
62 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
63 | "bootscript=echo Running bootscript from mmc ...; " \ | |
64 | "source ${loadaddr}\0" \ | |
65 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
66 | MMCARGS \ | |
67 | NANDARGS | |
68 | ||
69 | #define CONFIG_BOOTCOMMAND \ | |
70 | "mmc dev ${mmcdev}; if mmc rescan; then " \ | |
71 | "if run loadbootscript; then " \ | |
72 | "run bootscript; " \ | |
73 | "else " \ | |
74 | "if run loaduimage; then " \ | |
75 | "run mmcboot; " \ | |
76 | "else run nandboot; " \ | |
77 | "fi; " \ | |
78 | "fi; " \ | |
79 | "else run nandboot; fi" | |
80 | #endif /* CONFIG_SPL_BUILD */ | |
81 | ||
82 | #define CONFIG_TIMESTAMP | |
83 | #define CONFIG_SYS_AUTOLOAD "no" | |
84 | ||
85 | /* Serial console configuration */ | |
86 | #define CONFIG_CONS_INDEX 1 | |
87 | #define CONFIG_SERIAL1 1 /* UART0 */ | |
88 | ||
89 | /* NS16550 Configuration */ | |
90 | #define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0 */ | |
91 | #define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1 */ | |
54e7445d IL |
92 | |
93 | /* I2C Configuration */ | |
94 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */ | |
95 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
52658fda | 96 | #define CONFIG_SYS_I2C_EEPROM_BUS 0 |
54e7445d IL |
97 | |
98 | /* SPL */ | |
54e7445d IL |
99 | |
100 | /* Network. */ | |
54e7445d IL |
101 | #define CONFIG_PHY_ATHEROS |
102 | ||
103 | /* NAND support */ | |
104 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
105 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ | |
106 | CONFIG_SYS_NAND_PAGE_SIZE) | |
107 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
108 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
109 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
110 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
111 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
112 | 10, 11, 12, 13, 14, 15, 16, 17, \ | |
113 | 18, 19, 20, 21, 22, 23, 24, 25, \ | |
114 | 26, 27, 28, 29, 30, 31, 32, 33, \ | |
115 | 34, 35, 36, 37, 38, 39, 40, 41, \ | |
116 | 42, 43, 44, 45, 46, 47, 48, 49, \ | |
117 | 50, 51, 52, 53, 54, 55, 56, 57, } | |
118 | ||
119 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
120 | #define CONFIG_SYS_NAND_ECCBYTES 14 | |
121 | ||
122 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
123 | ||
124 | #undef CONFIG_SYS_NAND_U_BOOT_OFFS | |
125 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x200000 | |
126 | ||
54e7445d IL |
127 | #define CONFIG_ENV_OFFSET 0x300000 /* environment starts here */ |
128 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */ | |
129 | #define CONFIG_SYS_NAND_ONFI_DETECTION | |
434f2cfc | 130 | #ifdef CONFIG_SPL_OS_BOOT |
434f2cfc | 131 | #define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x500000 |
434f2cfc | 132 | #endif |
54e7445d IL |
133 | |
134 | /* GPIO pin + bank to pin ID mapping */ | |
135 | #define GPIO_PIN(_bank, _pin) ((_bank << 5) + _pin) | |
136 | ||
e8ac22be | 137 | /* Status LED */ |
e8ac22be | 138 | /* Status LED polarity is inversed, so init it in the "off" state */ |
e8ac22be | 139 | |
0e656b82 | 140 | /* EEPROM */ |
0e656b82 NK |
141 | #define CONFIG_ENV_EEPROM_IS_ON_I2C |
142 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
143 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 | |
144 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
145 | #define CONFIG_SYS_EEPROM_SIZE 256 | |
146 | ||
ef62df80 IL |
147 | #ifndef CONFIG_SPL_BUILD |
148 | /* | |
149 | * Enable PCA9555 at I2C0-0x26. | |
150 | * First select the I2C0 bus with "i2c dev 0", then use "pca953x" command. | |
151 | */ | |
152 | #define CONFIG_PCA953X | |
ef62df80 IL |
153 | #define CONFIG_SYS_I2C_PCA953X_ADDR 0x26 |
154 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x26, 16} } | |
155 | #endif /* CONFIG_SPL_BUILD */ | |
156 | ||
54e7445d IL |
157 | #endif /* __CONFIG_CM_T335_H */ |
158 |