[people/ms/u-boot.git] / include / configs / cobra5272.h

/*
 * Configuation settings for the Sentec Cobra Board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* ---
 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
 * Date: 2004-03-29
 * Author: Florian Schlote
 *
 * For a description of configuration options please refer also to the
 * general u-boot-1.x.x/README file
 * ---
 */

/* ---
 * board/config.h - configuration options, board specific
 * ---
 */

#ifndef _CONFIG_COBRA5272_H
#define _CONFIG_COBRA5272_H

/* ---
 * Defines processor clock - important for correct timings concerning serial
 * interface etc.
 * ---
 */

#define CONFIG_SYS_CLK			66000000
#define CONFIG_SYS_SDRAM_SIZE		16		/* SDRAM size in MB */

/* ---
 * Enable use of Ethernet
 * ---
 */
#define CONFIG_MCFFEC

/* Enable Dma Timer */
#define CONFIG_MCFTMR

/* ---
 * Define baudrate for UART1 (console output, tftp, ...)
 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
 * interface
 * ---
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

/* ---
 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
 * timeout acc. to your needs
 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
 * for 10 sec
 * ---
 */

#if 0
#define CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */
#endif

/* ---
 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
 * bootloader residing in flash ('chainloading'); if you want to use
 * chainloading or want to compile a u-boot binary that can be loaded into
 * RAM via BDM set
 *	"#if 0" to "#if 1"
 * You will need a first stage bootloader then, e. g. colilo or a working BDM
 * cable (Background Debug Mode)
 *
 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
 *
 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
 *
 * ---
 */

#if 0
#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
#endif

/* ---
 * Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 * ---
 */

#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/*
 *-----------------------------------------------------------------------------
 * Define user parameters that have to be customized most likely
 *-----------------------------------------------------------------------------
 */

/*AUTOBOOT settings - booting images automatically by u-boot after power on*/

/* The following settings will be contained in the environment block ; if you
want to use a neutral environment all those settings can be manually set in
u-boot: 'set' command */

#if 0

#define CONFIG_BOOTCOMMAND	"bootm 0xffe80000"	/*Autoboto command, please
enter a valid image address in flash */

/* User network settings */

#define CONFIG_IPADDR 192.168.100.2		/* default board IP address */
#define CONFIG_SERVERIP 192.168.100.1	/* default tftp server IP address */

#endif

#define CONFIG_SYS_LOAD_ADDR		0x20000		/*Defines default RAM address
from which user programs will be started */

/*---*/

#define CONFIG_SYS_LONGHELP				/* undef to save memory		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

/*
 *-----------------------------------------------------------------------------
 * End of user parameters to be customized
 *-----------------------------------------------------------------------------
 */

/* ---
 * Defines memory range for test
 * ---
 */

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

/* ---
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 * ---
 */

/* ---
 * Base register address
 * ---
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */

/* ---
 * System Conf. Reg. & System Protection Reg.
 * ---
 */

#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/* ---
 * Ethernet settings
 * ---
 */

#define CONFIG_SYS_DISCOVER_PHY
#define CONFIG_SYS_ENET_BD_BASE	0x780000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in internal SRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000

/*
 *-------------------------------------------------------------------------
 * RAM SIZE (is defined above)
 *-----------------------------------------------------------------------
 */

/* #define CONFIG_SYS_SDRAM_SIZE		16 */

/*
 *-----------------------------------------------------------------------
 */

#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	11	/* max number of sectors on one chip	*/
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000	/* flash timeout */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 *
 * Please refer also to Motorola Coldfire user manual - Chapter XXX
 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014

#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0

#define CONFIG_SYS_BR2_PRELIM		0
#define CONFIG_SYS_OR2_PRELIM		0

#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0

#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0

#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0

#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0

#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFF00007C

/*-----------------------------------------------------------------------
 * LED config
 */
#define	LED_STAT_0	0xffff /*all LEDs off*/
#define	LED_STAT_1	0xfffe
#define	LED_STAT_2	0xfffd
#define	LED_STAT_3	0xfffb
#define	LED_STAT_4	0xfff7
#define	LED_STAT_5	0xffef
#define	LED_STAT_6	0xffdf
#define	LED_STAT_7	0xff00 /*all LEDs on*/

/*-----------------------------------------------------------------------
 * Port configuration (GPIO)
 */
#define CONFIG_SYS_PACNT		0x00000000		/* PortA control reg.: All pins are external
GPIO*/
#define CONFIG_SYS_PADDR		0x00FF			/* PortA direction reg.: PA7 to PA0 are outputs
(1^=output, 0^=input) */
#define CONFIG_SYS_PADAT		LED_STAT_0		/* PortA value reg.: Turn all LED off */
#define CONFIG_SYS_PBCNT		0x55554155		/* PortB control reg.: Ethernet/UART
configuration */
#define CONFIG_SYS_PBDDR		0x0000			/* PortB direction: All pins configured as inputs */
#define CONFIG_SYS_PBDAT		0x0000			/* PortB value reg. */
#define CONFIG_SYS_PDCNT		0x00000000		/* PortD control reg. */

#endif	/* _CONFIG_COBRA5272_H */
Commit	Line	Data
a562e1bd WD	1	/*
	2	* Configuation settings for the Sentec Cobra Board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
a562e1bd WD	7	*/
	8
	9	/* ---
a187559e	10	* Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
a562e1bd WD	11	* Date: 2004-03-29
	12	* Author: Florian Schlote
	13	*
	14	* For a description of configuration options please refer also to the
	15	* general u-boot-1.x.x/README file
	16	* ---
	17	*/
	18
	19	/* ---
	20	* board/config.h - configuration options, board specific
	21	* ---
	22	*/
	23
	24	#ifndef _CONFIG_COBRA5272_H
	25	#define _CONFIG_COBRA5272_H
	26
a562e1bd WD	27	/* ---
	28	* Defines processor clock - important for correct timings concerning serial
	29	* interface etc.
a562e1bd WD	30	* ---
	31	*/
	32
6d0f6bcf JCPV	33	#define CONFIG_SYS_CLK 66000000
6d0f6bcf JCPV	34	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
a562e1bd WD	35
	36	/* ---
	37	* Enable use of Ethernet
	38	* ---
	39	*/
6706424d	40	#define CONFIG_MCFFEC
a562e1bd	41
6706424d TL	42	/* Enable Dma Timer */
6706424d TL	43	#define CONFIG_MCFTMR
a562e1bd WD	44
	45	/* ---
	46	* Define baudrate for UART1 (console output, tftp, ...)
	47	* default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
6d0f6bcf	48	* CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
a562e1bd WD	49	* interface
	50	* ---
	51	*/
	52
6706424d	53	#define CONFIG_MCFUART
6d0f6bcf	54	#define CONFIG_SYS_UART_PORT (0)
a562e1bd WD	55
	56	/* ---
	57	* set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
	58	* timeout acc. to your needs
	59	* #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
	60	* for 10 sec
	61	* ---
	62	*/
	63
	64	#if 0
	65	#define CONFIG_WATCHDOG
	66	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
	67	#endif
	68
	69	/* ---
	70	* CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
	71	* bootloader residing in flash ('chainloading'); if you want to use
	72	* chainloading or want to compile a u-boot binary that can be loaded into
	73	* RAM via BDM set
53677ef1	74	* "#if 0" to "#if 1"
a562e1bd WD	75	* You will need a first stage bootloader then, e. g. colilo or a working BDM
	76	* cable (Background Debug Mode)
	77	*
	78	* Setting #if 0: u-boot will start from flash and relocate itself to RAM
	79	*
14d0a02a	80	* Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
a562e1bd WD	81	* in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
	82	*
	83	* ---
	84	*/
	85
	86	#if 0
	87	#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
	88	#endif
	89
	90	/* ---
	91	* Configuration for environment
	92	* Environment is embedded in u-boot in the second sector of the flash
	93	* ---
	94	*/
	95
	96	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	97	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	98	#define CONFIG_ENV_SECT_SIZE 0x2000
a562e1bd	99	#else
0e8d1586 JCPV	100	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	101	#define CONFIG_ENV_SECT_SIZE 0x2000
a562e1bd WD	102	#endif
a562e1bd WD	103
5296cb1d	104	#define LDS_BOARD_TEXT \
0649cd0d SG	105	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	106	env/embedded.o(.text);
37e4f24b	107
80ff4f99 JL	108	/*
	109	* BOOTP options
	110	*/
	111	#define CONFIG_BOOTP_BOOTFILESIZE
	112	#define CONFIG_BOOTP_BOOTPATH
	113	#define CONFIG_BOOTP_GATEWAY
	114	#define CONFIG_BOOTP_HOSTNAME
	115
37e4f24b JL	116	/*
37e4f24b JL	117	* Command line configuration.
a562e1bd WD	118	*/
a562e1bd WD	119
6706424d	120	#ifdef CONFIG_MCFFEC
6706424d	121	# define CONFIG_MII 1
0f3ba7e9	122	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	123	# define CONFIG_SYS_DISCOVER_PHY
	124	# define CONFIG_SYS_RX_ETH_BUFFER 8
	125	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	126
6d0f6bcf JCPV	127	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	128	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	129	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	130	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	131	# ifndef CONFIG_SYS_DISCOVER_PHY
6706424d TL	132	# define FECDUPLEX FULL
	133	# define FECSPEED _100BASET
	134	# else
6d0f6bcf JCPV	135	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	136	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6706424d	137	# endif
6d0f6bcf	138	# endif /* CONFIG_SYS_DISCOVER_PHY */
6706424d	139	#endif
a562e1bd WD	140
	141	/*
	142	*-----------------------------------------------------------------------------
	143	* Define user parameters that have to be customized most likely
	144	*-----------------------------------------------------------------------------
	145	*/
	146
	147	/AUTOBOOT settings - booting images automatically by u-boot after power on/
	148
a562e1bd WD	149	/* The following settings will be contained in the environment block ; if you
	150	want to use a neutral environment all those settings can be manually set in
	151	u-boot: 'set' command */
	152
	153	#if 0
	154
	155	#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
	156	enter a valid image address in flash */
	157
a562e1bd WD	158	/* User network settings */
a562e1bd WD	159
a562e1bd WD	160	#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
	161	#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
	162
	163	#endif
	164
6d0f6bcf	165	#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
a562e1bd WD	166	from which user programs will be started */
	167
	168	/---/
	169
6d0f6bcf	170	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a562e1bd	171
37e4f24b	172	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	173	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a562e1bd	174	#else
6d0f6bcf	175	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a562e1bd	176	#endif
6d0f6bcf JCPV	177	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	178	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	179	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a562e1bd WD	180
	181	/*
	182	*-----------------------------------------------------------------------------
	183	* End of user parameters to be customized
	184	*-----------------------------------------------------------------------------
	185	*/
	186
	187	/* ---
	188	* Defines memory range for test
	189	* ---
	190	*/
	191
6d0f6bcf JCPV	192	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	193	#define CONFIG_SYS_MEMTEST_END 0x380000
a562e1bd WD	194
	195	/* ---
	196	* Low Level Configuration Settings
	197	* (address mappings, register initial values, etc.)
	198	* You should know what you are doing if you make changes here.
	199	* ---
	200	*/
	201
	202	/* ---
	203	* Base register address
	204	* ---
	205	*/
	206
6d0f6bcf	207	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
a562e1bd WD	208
	209	/* ---
	210	* System Conf. Reg. & System Protection Reg.
	211	* ---
	212	*/
	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_SCR 0x0003
6d0f6bcf JCPV	215	#define CONFIG_SYS_SPR 0xffff
a562e1bd WD	216
	217	/* ---
	218	* Ethernet settings
	219	* ---
	220	*/
	221
6d0f6bcf JCPV	222	#define CONFIG_SYS_DISCOVER_PHY
6d0f6bcf JCPV	223	#define CONFIG_SYS_ENET_BD_BASE 0x780000
a562e1bd WD	224
	225	/*-----------------------------------------------------------------------
	226	* Definitions for initial stack pointer and data area (in internal SRAM)
	227	*/
6d0f6bcf	228	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	229	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	230	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	231	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a562e1bd WD	232
	233	/*-----------------------------------------------------------------------
	234	* Start addresses for the final memory configuration
	235	* (Set up by the startup code)
6d0f6bcf	236	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a562e1bd	237	*/
6d0f6bcf	238	#define CONFIG_SYS_SDRAM_BASE 0x00000000
a562e1bd WD	239
	240	/*
	241	*-------------------------------------------------------------------------
	242	* RAM SIZE (is defined above)
	243	*-----------------------------------------------------------------------
	244	*/
	245
6d0f6bcf	246	/* #define CONFIG_SYS_SDRAM_SIZE 16 */
a562e1bd WD	247
	248	/*
	249	*-----------------------------------------------------------------------
	250	*/
	251
6d0f6bcf	252	#define CONFIG_SYS_FLASH_BASE 0xffe00000
a562e1bd WD	253
a562e1bd WD	254	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	255	#define CONFIG_SYS_MONITOR_BASE 0x20000
a562e1bd	256	#else
6d0f6bcf	257	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a562e1bd WD	258	#endif
a562e1bd WD	259
6d0f6bcf JCPV	260	#define CONFIG_SYS_MONITOR_LEN 0x20000
	261	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	262	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
a562e1bd WD	263
	264	/*
	265	* For booting Linux, the board info and command line data
	266	* have to be in the first 8 MB of memory, since this is
	267	* the maximum mapped by the Linux kernel during initialization ??
	268	*/
6d0f6bcf	269	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
a562e1bd WD	270
	271	/*-----------------------------------------------------------------------
	272	* FLASH organization
	273	*/
6d0f6bcf JCPV	274	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	275	#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
	276	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
a562e1bd WD	277
	278	/*-----------------------------------------------------------------------
	279	* Cache Configuration
	280	*/
6d0f6bcf	281	#define CONFIG_SYS_CACHELINE_SIZE 16
a562e1bd	282
dd9f054e	283	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	284	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	285	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	286	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	287	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	288	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	289	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	290	CF_ACR_EN \| CF_ACR_SM_ALL)
	291	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	292	CF_CACR_DISD \| CF_CACR_INVI \| \
	293	CF_CACR_CEIB \| CF_CACR_DCM \| \
	294	CF_CACR_EUSP)
	295
a562e1bd WD	296	/*-----------------------------------------------------------------------
	297	* Memory bank definitions
	298	*
	299	* Please refer also to Motorola Coldfire user manual - Chapter XXX
	300	* <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
	301	*/
6d0f6bcf JCPV	302	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
6d0f6bcf JCPV	303	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
a562e1bd	304
6d0f6bcf JCPV	305	#define CONFIG_SYS_BR1_PRELIM 0
6d0f6bcf JCPV	306	#define CONFIG_SYS_OR1_PRELIM 0
a562e1bd	307
6d0f6bcf JCPV	308	#define CONFIG_SYS_BR2_PRELIM 0
6d0f6bcf JCPV	309	#define CONFIG_SYS_OR2_PRELIM 0
a562e1bd	310
6d0f6bcf JCPV	311	#define CONFIG_SYS_BR3_PRELIM 0
6d0f6bcf JCPV	312	#define CONFIG_SYS_OR3_PRELIM 0
a562e1bd	313
6d0f6bcf JCPV	314	#define CONFIG_SYS_BR4_PRELIM 0
6d0f6bcf JCPV	315	#define CONFIG_SYS_OR4_PRELIM 0
a562e1bd	316
6d0f6bcf JCPV	317	#define CONFIG_SYS_BR5_PRELIM 0
6d0f6bcf JCPV	318	#define CONFIG_SYS_OR5_PRELIM 0
a562e1bd	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_BR6_PRELIM 0
6d0f6bcf JCPV	321	#define CONFIG_SYS_OR6_PRELIM 0
a562e1bd	322
6d0f6bcf JCPV	323	#define CONFIG_SYS_BR7_PRELIM 0x00000701
6d0f6bcf JCPV	324	#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
a562e1bd WD	325
	326	/*-----------------------------------------------------------------------
	327	* LED config
	328	*/
	329	#define LED_STAT_0 0xffff /all LEDs off/
	330	#define LED_STAT_1 0xfffe
	331	#define LED_STAT_2 0xfffd
	332	#define LED_STAT_3 0xfffb
	333	#define LED_STAT_4 0xfff7
	334	#define LED_STAT_5 0xffef
	335	#define LED_STAT_6 0xffdf
	336	#define LED_STAT_7 0xff00 /all LEDs on/
	337
	338	/*-----------------------------------------------------------------------
	339	* Port configuration (GPIO)
	340	*/
6d0f6bcf	341	#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
a562e1bd	342	GPIO*/
6d0f6bcf	343	#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
a562e1bd	344	(1^=output, 0^=input) */
6d0f6bcf JCPV	345	#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
6d0f6bcf JCPV	346	#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
a562e1bd	347	configuration */
6d0f6bcf JCPV	348	#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
	349	#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
	350	#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
a562e1bd WD	351
a562e1bd WD	352	#endif /* _CONFIG_COBRA5272_H */