[people/ms/u-boot.git] / include / configs / cogent_mpc8xx.h

/*
 * (C) Copyright 2000-2010
 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * Config header file for Cogent platform using an MPC8xx CPU module
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is an MPC860 CPU	*/
#define CONFIG_COGENT		1	/* using Cogent Modular Architecture */

#define	CONFIG_SYS_TEXT_BASE	0xfff00000

#define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
#define	CONFIG_MISC_INIT_R		/* Use misc_init_r()		*/

/* Cogent Modular Architecture options */
#define CONFIG_CMA286_60_OLD	1	/* ...on an old CMA286-60 CPU module */
#define CONFIG_CMA102		1	/* ...on a CMA102 motherboard	*/
#define CONFIG_CMA302		1	/* ...with a CMA302 flash I/O module */

/* serial console configuration */
#undef	CONFIG_8xx_CONS_SMC1
#undef	CONFIG_8xx_CONS_SMC2
#define CONFIG_8xx_CONS_NONE	/* not on 8xx serial ports (eg on cogent m/b) */

#if defined(CONFIG_CMA286_60_OLD)
#define CONFIG_8xx_GCLK_FREQ	33333000 /* define if cant use get_gclk_freq */
#endif

#define CONFIG_BAUDRATE		230400

#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		400000  /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE		0x7F


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_KGDB
#define CONFIG_CMD_I2C

#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootm 04080000 04200000" /* autoboot command*/

#define CONFIG_BOOTARGS		"root=/dev/ram rw"

#if defined(CONFIG_CMD_KGDB)
#undef	CONFIG_KGDB_ON_SMC		/* define if kgdb on SMC */
#undef	CONFIG_KGDB_ON_SCC		/* define if kgdb on SCC */
#define	CONFIG_KGDB_NONE		/* define if kgdb on something else */
#define CONFIG_KGDB_INDEX	2	/* which SMC/SCC channel for kgdb */
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

#define CONFIG_WATCHDOG			/* turn on platform specific watchdog */

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x01c00000	/* 4 ... 28 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }

#define CONFIG_SYS_ALLOC_DPRAM

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Low Level Cogent settings
 * if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
 * also, make sure CONFIG_CONS_INDEX is still defined - the index will be
 * 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
 * (second 2 for CMA120 only)
 */
#define CONFIG_SYS_CMA_MB_BASE		0x00000000	/* base of m/b address space */

#include <configs/cogent_common.h>

#define CONFIG_SYS_CMA_CONS_SERIAL	/* use Cogent motherboard serial for console */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_CMA_LCD_HEARTBEAT	/* define for sec rotator in lcd corner */
#define CONFIG_SHOW_ACTIVITY
#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
/*
 * flash exists on the motherboard
 * set these four according to TOP dipsw:
 * TOP on  => ..._FLLOW_...	(boot EPROM space is high so FLASH is low )
 * TOP off => ..._FLHIGH_...	(boot EPROM space is low  so FLASH is high)
 */
#define CMA_MB_FLASH_EXEC_BASE	CMA_MB_FLLOW_EXEC_BASE
#define CMA_MB_FLASH_EXEC_SIZE	CMA_MB_FLLOW_EXEC_SIZE
#define CMA_MB_FLASH_RDWR_BASE	CMA_MB_FLLOW_RDWR_BASE
#define CMA_MB_FLASH_RDWR_SIZE	CMA_MB_FLLOW_RDWR_SIZE
#endif
#define CMA_MB_FLASH_BASE	CMA_MB_FLASH_EXEC_BASE
#define CMA_MB_FLASH_SIZE	CMA_MB_FLASH_EXEC_SIZE

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		CMA_MB_RAM_BASE
#ifdef CONFIG_CMA302
#define CONFIG_SYS_FLASH_BASE		CMA_MB_SLOT2_BASE	/* cma302 in slot 2 */
#else
#define CONFIG_SYS_FLASH_BASE		CMA_MB_FLASH_BASE	/* flash on m/b */
#endif
#define	CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 128 kB for Monitor	*/
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
#ifdef CONFIG_CMA302
#define	CONFIG_ENV_SIZE		0x1000	/* Total Size of Environment Sector	*/
#define CONFIG_ENV_SECT_SIZE	(512*1024) /* see README - env sect real size */
#else
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#endif
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif


/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif	/* CONFIG_WATCHDOG */

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | SCCR_RTDIV    | SCCR_RTSEL    | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

#if defined(CONFIG_CMA286_60_OLD)

/*
 * Init Memory Controller:
 *
 * NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
 * they are actually the final settings for this cpu/board, because the
 * flash and RAM are on the motherboard, accessed via the CMAbus, and the
 * mappings are pretty much fixed.
 *
 * (the *_SIZE vars must be a power of 2)
 */

#define CONFIG_SYS_CMA_CS0_BASE	CONFIG_SYS_TEXT_BASE		/* EPROM */
#define CONFIG_SYS_CMA_CS0_SIZE	(1 << 20)
#define CONFIG_SYS_CMA_CS1_BASE	CMA_MB_RAM_BASE		/* RAM + I/O SLOT 1 */
#define CONFIG_SYS_CMA_CS1_SIZE	(64 << 20)
#define CONFIG_SYS_CMA_CS2_BASE	CMA_MB_SLOT2_BASE	/* I/O SLOTS 2 + 3 */
#define CONFIG_SYS_CMA_CS2_SIZE	(64 << 20)
#define CONFIG_SYS_CMA_CS3_BASE	CMA_MB_ROMLOW_BASE	/* M/B I/O */
#define CONFIG_SYS_CMA_CS3_SIZE	(32 << 20)

/*
 * CS0 maps the EPROM on the cpu module
 * Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
 *
 * Note: We must have already transferred control to the final location
 * of the EPROM before these are used, because when BR0/OR0 are set, the
 * mirror of the eprom at any other addresses will disappear.
 */

/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)|BR_PS_16|BR_WP|BR_V)
/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SCY_4_CLK)

/*
 * CS1 maps motherboard DRAM and motherboard I/O slot 1
 * (each 32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR1_PRELIM	((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
#define CONFIG_SYS_OR1_PRELIM	((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)|OR_SETA)

/*
 * CS2 maps motherboard I/O slots 2 and 3
 * (each 32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR2_PRELIM	((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
#define CONFIG_SYS_OR2_PRELIM	((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)|OR_SETA)

/*
 * CS3 maps motherboard I/O
 * (32Mbyte in size)
 */

/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)|BR_V)
/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
#define CONFIG_SYS_OR3_PRELIM	((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)|OR_BI|OR_SETA)

#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768	1	/*
cd0402a7	2	* (C) Copyright 2000-2010
0f8c9768 WD	3	* Murray Jensen <Murray.Jensen@cmst.csiro.au>
0f8c9768 WD	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0f8c9768 WD	6	*/
	7
	8	/*
	9	* Config header file for Cogent platform using an MPC8xx CPU module
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC860 1 /* This is an MPC860 CPU */
	21	#define CONFIG_COGENT 1 /* using Cogent Modular Architecture */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xfff00000
2ae18241 WD	24
c837dcb1	25	#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
3a8f28d0	26	#define CONFIG_MISC_INIT_R /* Use misc_init_r() */
c837dcb1	27
0f8c9768 WD	28	/* Cogent Modular Architecture options */
	29	#define CONFIG_CMA286_60_OLD 1 /* ...on an old CMA286-60 CPU module */
	30	#define CONFIG_CMA102 1 /* ...on a CMA102 motherboard */
	31	#define CONFIG_CMA302 1 /* ...with a CMA302 flash I/O module */
	32
	33	/* serial console configuration */
	34	#undef CONFIG_8xx_CONS_SMC1
	35	#undef CONFIG_8xx_CONS_SMC2
	36	#define CONFIG_8xx_CONS_NONE /* not on 8xx serial ports (eg on cogent m/b) */
	37
	38	#if defined(CONFIG_CMA286_60_OLD)
	39	#define CONFIG_8xx_GCLK_FREQ 33333000 /* define if cant use get_gclk_freq */
	40	#endif
	41
	42	#define CONFIG_BAUDRATE 230400
	43
	44	#define CONFIG_HARD_I2C /* I2C with hardware support */
6d0f6bcf JCPV	45	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	46	#define CONFIG_SYS_I2C_SLAVE 0x7F
0f8c9768 WD	47
0f8c9768 WD	48
80ff4f99 JL	49	/*
	50	* BOOTP options
	51	*/
	52	#define CONFIG_BOOTP_BOOTFILESIZE
	53	#define CONFIG_BOOTP_BOOTPATH
	54	#define CONFIG_BOOTP_GATEWAY
	55	#define CONFIG_BOOTP_HOSTNAME
	56
	57
37e4f24b JL	58	/*
	59	* Command line configuration.
	60	*/
	61	#include <config_cmd_default.h>
	62
	63	#define CONFIG_CMD_KGDB
	64	#define CONFIG_CMD_I2C
	65
	66	#undef CONFIG_CMD_NET
cd0402a7	67	#undef CONFIG_CMD_NFS
0f8c9768 WD	68
	69	#if 0
	70	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	71	#else
	72	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	73	#endif
	74	#define CONFIG_BOOTCOMMAND "bootm 04080000 04200000" /* autoboot command*/
	75
	76	#define CONFIG_BOOTARGS "root=/dev/ram rw"
	77
37e4f24b	78	#if defined(CONFIG_CMD_KGDB)
0f8c9768 WD	79	#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
	80	#undef CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
	81	#define CONFIG_KGDB_NONE /* define if kgdb on something else */
	82	#define CONFIG_KGDB_INDEX 2 /* which SMC/SCC channel for kgdb */
	83	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	84	#endif
	85
	86	#define CONFIG_WATCHDOG /* turn on platform specific watchdog */
	87
	88	/*
	89	* Miscellaneous configurable options
	90	*/
6d0f6bcf JCPV	91	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	92	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
37e4f24b	93	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	94	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	95	#else
6d0f6bcf	96	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	97	#endif
6d0f6bcf JCPV	98	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	99	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	100	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */
6d0f6bcf JCPV	103	#define CONFIG_SYS_MEMTEST_END 0x01c00000 /* 4 ... 28 MB in DRAM */
0f8c9768	104
6d0f6bcf	105	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
0f8c9768	106
6d0f6bcf	107	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
0f8c9768	108
6d0f6bcf	109	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
0f8c9768	110
6d0f6bcf	111	#define CONFIG_SYS_ALLOC_DPRAM
0f8c9768 WD	112
	113	/*
	114	* Low Level Configuration Settings
	115	* (address mappings, register initial values, etc.)
	116	* You should know what you are doing if you make changes here.
	117	*/
	118
	119	/*-----------------------------------------------------------------------
	120	* Low Level Cogent settings
6d0f6bcf	121	* if CONFIG_SYS_CMA_CONS_SERIAL is defined, make sure the 8xx CPM serial is not.
0f8c9768 WD	122	* also, make sure CONFIG_CONS_INDEX is still defined - the index will be
	123	* 1 for serialA, 2 for serialB, 3 for ser2A, 4 for ser2B
	124	* (second 2 for CMA120 only)
	125	*/
6d0f6bcf	126	#define CONFIG_SYS_CMA_MB_BASE 0x00000000 /* base of m/b address space */
0f8c9768 WD	127
	128	#include <configs/cogent_common.h>
	129
6d0f6bcf	130	#define CONFIG_SYS_CMA_CONS_SERIAL /* use Cogent motherboard serial for console */
0f8c9768	131	#define CONFIG_CONS_INDEX 1
6d0f6bcf	132	#define CONFIG_SYS_CMA_LCD_HEARTBEAT /* define for sec rotator in lcd corner */
a8c7c708	133	#define CONFIG_SHOW_ACTIVITY
0f8c9768 WD	134	#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
	135	/*
	136	* flash exists on the motherboard
	137	* set these four according to TOP dipsw:
	138	* TOP on => ..._FLLOW_... (boot EPROM space is high so FLASH is low )
	139	* TOP off => ..._FLHIGH_... (boot EPROM space is low so FLASH is high)
	140	*/
	141	#define CMA_MB_FLASH_EXEC_BASE CMA_MB_FLLOW_EXEC_BASE
	142	#define CMA_MB_FLASH_EXEC_SIZE CMA_MB_FLLOW_EXEC_SIZE
	143	#define CMA_MB_FLASH_RDWR_BASE CMA_MB_FLLOW_RDWR_BASE
	144	#define CMA_MB_FLASH_RDWR_SIZE CMA_MB_FLLOW_RDWR_SIZE
	145	#endif
	146	#define CMA_MB_FLASH_BASE CMA_MB_FLASH_EXEC_BASE
	147	#define CMA_MB_FLASH_SIZE CMA_MB_FLASH_EXEC_SIZE
	148
	149	/*-----------------------------------------------------------------------
	150	* Internal Memory Mapped Register
	151	*/
6d0f6bcf	152	#define CONFIG_SYS_IMMR 0xFF000000
0f8c9768 WD	153
	154	/*-----------------------------------------------------------------------
	155	* Definitions for initial stack pointer and data area (in DPRAM)
	156	*/
6d0f6bcf	157	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	158	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	159	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	160	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	161
	162	/*-----------------------------------------------------------------------
	163	* Start addresses for the final memory configuration
	164	* (Set up by the startup code)
6d0f6bcf	165	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	166	*/
6d0f6bcf	167	#define CONFIG_SYS_SDRAM_BASE CMA_MB_RAM_BASE
0f8c9768	168	#ifdef CONFIG_CMA302
6d0f6bcf	169	#define CONFIG_SYS_FLASH_BASE CMA_MB_SLOT2_BASE /* cma302 in slot 2 */
0f8c9768	170	#else
6d0f6bcf	171	#define CONFIG_SYS_FLASH_BASE CMA_MB_FLASH_BASE /* flash on m/b */
0f8c9768	172	#endif
14d0a02a	173	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf JCPV	174	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
6d0f6bcf JCPV	175	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	176
	177	/*
	178	* For booting Linux, the board info and command line data
	179	* have to be in the first 8 MB of memory, since this is
	180	* the maximum mapped by the Linux kernel during initialization.
	181	*/
6d0f6bcf	182	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	183	/*-----------------------------------------------------------------------
	184	* FLASH organization
	185	*/
6d0f6bcf JCPV	186	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	187	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
0f8c9768	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	190	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	191
5a1aceb0	192	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	193	#define CONFIG_ENV_ADDR CONFIG_SYS_FLASH_BASE /* Addr of Environment Sector */
0f8c9768	194	#ifdef CONFIG_CMA302
0e8d1586 JCPV	195	#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
0e8d1586 JCPV	196	#define CONFIG_ENV_SECT_SIZE (5121024) / see README - env sect real size */
0f8c9768	197	#else
0e8d1586	198	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
0f8c9768 WD	199	#endif
	200	/*-----------------------------------------------------------------------
	201	* Cache Configuration
	202	*/
6d0f6bcf	203	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
37e4f24b	204	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	205	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	206	#endif
	207
	208
	209	/*-----------------------------------------------------------------------
	210	* SYPCR - System Protection Control 11-9
	211	* SYPCR can only be written once after reset!
	212	*-----------------------------------------------------------------------
	213	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	214	*/
	215	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	216	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	217	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768 WD	218	#else
6d0f6bcf	219	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	220	#endif /* CONFIG_WATCHDOG */
	221
	222	/*-----------------------------------------------------------------------
	223	* SIUMCR - SIU Module Configuration 11-6
	224	*-----------------------------------------------------------------------
	225	* PCMCIA config., multi-function pin tri-state
	226	*/
6d0f6bcf	227	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
0f8c9768 WD	228
	229	/*-----------------------------------------------------------------------
	230	* TBSCR - Time Base Status and Control 11-26
	231	*-----------------------------------------------------------------------
	232	* Clear Reference Interrupt Status, Timebase freezing enabled
	233	*/
6d0f6bcf	234	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0f8c9768 WD	235
	236	/*-----------------------------------------------------------------------
	237	* PISCR - Periodic Interrupt Status and Control 11-31
	238	*-----------------------------------------------------------------------
	239	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	240	*/
6d0f6bcf	241	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	242
	243	/*-----------------------------------------------------------------------
	244	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	245	*-----------------------------------------------------------------------
	246	* Reset PLL lock status sticky bit, timer expired status bit and timer
	247	* interrupt status bit - leave PLL multiplication factor unchanged !
	248	*/
6d0f6bcf	249	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
0f8c9768 WD	250
	251	/*-----------------------------------------------------------------------
	252	* SCCR - System Clock and reset Control Register 15-27
	253	*-----------------------------------------------------------------------
	254	* Set clock output, timebase and RTC source and divider,
	255	* power management and some other internal clocks
	256	*/
	257	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	258	#define CONFIG_SYS_SCCR (SCCR_TBS \| SCCR_RTDIV \| SCCR_RTSEL \| \
0f8c9768 WD	259	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	260	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	261	SCCR_DFALCD00)
	262
	263	/*-----------------------------------------------------------------------
	264	* PCMCIA stuff
	265	*-----------------------------------------------------------------------
	266	*
	267	*/
6d0f6bcf JCPV	268	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	269	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	270	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	271	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	272	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	273	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	274	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	275	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768 WD	276
	277	/*-----------------------------------------------------------------------
	278	*
	279	*-----------------------------------------------------------------------
	280	*
	281	*/
6d0f6bcf JCPV	282	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	283	#define CONFIG_SYS_DER 0
0f8c9768 WD	284
	285	#if defined(CONFIG_CMA286_60_OLD)
	286
	287	/*
	288	* Init Memory Controller:
	289	*
6d0f6bcf	290	* NOTE: although the names (CONFIG_SYS_xRn_PRELIM) suggest preliminary settings,
0f8c9768 WD	291	* they are actually the final settings for this cpu/board, because the
	292	* flash and RAM are on the motherboard, accessed via the CMAbus, and the
	293	* mappings are pretty much fixed.
	294	*
	295	* (the *_SIZE vars must be a power of 2)
	296	*/
	297
14d0a02a	298	#define CONFIG_SYS_CMA_CS0_BASE CONFIG_SYS_TEXT_BASE /* EPROM */
6d0f6bcf JCPV	299	#define CONFIG_SYS_CMA_CS0_SIZE (1 << 20)
	300	#define CONFIG_SYS_CMA_CS1_BASE CMA_MB_RAM_BASE /* RAM + I/O SLOT 1 */
	301	#define CONFIG_SYS_CMA_CS1_SIZE (64 << 20)
	302	#define CONFIG_SYS_CMA_CS2_BASE CMA_MB_SLOT2_BASE /* I/O SLOTS 2 + 3 */
	303	#define CONFIG_SYS_CMA_CS2_SIZE (64 << 20)
	304	#define CONFIG_SYS_CMA_CS3_BASE CMA_MB_ROMLOW_BASE /* M/B I/O */
	305	#define CONFIG_SYS_CMA_CS3_SIZE (32 << 20)
0f8c9768 WD	306
	307	/*
	308	* CS0 maps the EPROM on the cpu module
6d0f6bcf	309	* Set it for 4 wait states, address CONFIG_SYS_MONITOR_BASE and size 1M
0f8c9768 WD	310	*
	311	* Note: We must have already transferred control to the final location
	312	* of the EPROM before these are used, because when BR0/OR0 are set, the
	313	* mirror of the eprom at any other addresses will disappear.
	314	*/
	315
6d0f6bcf JCPV	316	/* base address = CONFIG_SYS_CMA_CS0_BASE, 16-bit, no parity, r/o, gpcm */
	317	#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_CMA_CS0_BASE&BR_BA_MSK)\|BR_PS_16\|BR_WP\|BR_V)
	318	/* mask size CONFIG_SYS_CMA_CS0_SIZE, CS time normal, burst inhibit, 4-wait states */
	319	#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_CMA_CS0_SIZE-1)&OR_AM_MSK)\|OR_BI\|OR_SCY_4_CLK)
0f8c9768 WD	320
	321	/*
	322	* CS1 maps motherboard DRAM and motherboard I/O slot 1
	323	* (each 32Mbyte in size)
	324	*/
	325
6d0f6bcf JCPV	326	/* base address = CONFIG_SYS_CMA_CS1_BASE, 32-bit, no parity, r/w, gpcm */
	327	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_CMA_CS1_BASE&BR_BA_MSK)\|BR_V)
	328	/* mask size CONFIG_SYS_CMA_CS1_SIZE, CS time normal, burst ok, ext xfer ack */
	329	#define CONFIG_SYS_OR1_PRELIM ((~(CONFIG_SYS_CMA_CS1_SIZE-1)&OR_AM_MSK)\|OR_SETA)
0f8c9768 WD	330
	331	/*
	332	* CS2 maps motherboard I/O slots 2 and 3
	333	* (each 32Mbyte in size)
	334	*/
	335
6d0f6bcf JCPV	336	/* base address = CONFIG_SYS_CMA_CS2_BASE, 32-bit, no parity, r/w, gpcm */
	337	#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_CMA_CS2_BASE&BR_BA_MSK)\|BR_V)
	338	/* mask size CONFIG_SYS_CMA_CS2_SIZE, CS time normal, burst ok, ext xfer ack */
	339	#define CONFIG_SYS_OR2_PRELIM ((~(CONFIG_SYS_CMA_CS2_SIZE-1)&OR_AM_MSK)\|OR_SETA)
0f8c9768 WD	340
	341	/*
	342	* CS3 maps motherboard I/O
	343	* (32Mbyte in size)
	344	*/
	345
6d0f6bcf JCPV	346	/* base address = CONFIG_SYS_CMA_CS3_BASE, 32-bit, no parity, r/w, gpcm */
	347	#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_CMA_CS3_BASE&BR_BA_MSK)\|BR_V)
	348	/* mask size CONFIG_SYS_CMA_CS3_SIZE, CS time normal, burst inhibit, ext xfer ack */
	349	#define CONFIG_SYS_OR3_PRELIM ((~(CONFIG_SYS_CMA_CS3_SIZE-1)&OR_AM_MSK)\|OR_BI\|OR_SETA)
0f8c9768 WD	350
0f8c9768 WD	351	#endif
0f8c9768	352	#endif /* __CONFIG_H */