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2e49984b MV |
1 | /* |
2 | * Toradex Colibri PXA270 configuration file | |
3 | * | |
4 | * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> | |
b891d010 | 5 | * Copyright (C) 2015-2016 Marcel Ziswiler <marcel@ziswiler.com> |
2e49984b | 6 | * |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
2e49984b MV |
8 | */ |
9 | ||
7c49b523 MZ |
10 | #ifndef __CONFIG_H |
11 | #define __CONFIG_H | |
2e49984b MV |
12 | |
13 | /* | |
14 | * High Level Board Configuration Options | |
15 | */ | |
abc20aba | 16 | #define CONFIG_CPU_PXA27X 1 /* Marvell PXA270 CPU */ |
7c49b523 MZ |
17 | /* Avoid overwriting factory configuration block */ |
18 | #define CONFIG_BOARD_SIZE_LIMIT 0x40000 | |
2e49984b | 19 | |
4f9bbd9e MZ |
20 | /* We will never enable dcache because we have to setup MMU first */ |
21 | #define CONFIG_SYS_DCACHE_OFF | |
22 | ||
b891d010 MZ |
23 | #define CONFIG_DISPLAY_BOARDINFO_LATE /* Calls show_board_info() */ |
24 | ||
2e49984b MV |
25 | /* |
26 | * Environment settings | |
27 | */ | |
f9f5486c | 28 | #define CONFIG_ENV_OVERWRITE |
b891d010 | 29 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
f9f5486c MV |
30 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) |
31 | #define CONFIG_ARCH_CPU_INIT | |
2e49984b | 32 | #define CONFIG_BOOTCOMMAND \ |
99d672fa | 33 | "if fatload mmc 0 0xa0000000 uImage; then " \ |
2e49984b MV |
34 | "bootm 0xa0000000; " \ |
35 | "fi; " \ | |
36 | "if usb reset && fatload usb 0 0xa0000000 uImage; then " \ | |
37 | "bootm 0xa0000000; " \ | |
38 | "fi; " \ | |
99d672fa | 39 | "bootm 0xc0000;" |
2e49984b | 40 | #define CONFIG_TIMESTAMP |
2e49984b MV |
41 | #define CONFIG_CMDLINE_TAG |
42 | #define CONFIG_SETUP_MEMORY_TAGS | |
2e49984b MV |
43 | |
44 | /* | |
45 | * Serial Console Configuration | |
46 | */ | |
2e49984b MV |
47 | |
48 | /* | |
49 | * Bootloader Components Configuration | |
50 | */ | |
2e49984b | 51 | |
3664fa1b MZ |
52 | /* I2C support */ |
53 | #ifdef CONFIG_SYS_I2C | |
3664fa1b MZ |
54 | #define CONFIG_SYS_I2C_PXA |
55 | #define CONFIG_PXA_STD_I2C | |
56 | #define CONFIG_PXA_PWR_I2C | |
57 | #define CONFIG_SYS_I2C_SPEED 100000 | |
58 | #endif | |
59 | ||
4f9bbd9e MZ |
60 | /* LCD support */ |
61 | #ifdef CONFIG_LCD | |
62 | #define CONFIG_PXA_LCD | |
63 | #define CONFIG_PXA_VGA | |
4f9bbd9e MZ |
64 | #define CONFIG_LCD_LOGO |
65 | #endif | |
66 | ||
2e49984b MV |
67 | /* |
68 | * Networking Configuration | |
2e49984b MV |
69 | */ |
70 | #ifdef CONFIG_CMD_NET | |
2e49984b | 71 | |
2e49984b MV |
72 | #define CONFIG_DRIVER_DM9000 1 |
73 | #define CONFIG_DM9000_BASE 0x08000000 | |
74 | #define DM9000_IO (CONFIG_DM9000_BASE) | |
75 | #define DM9000_DATA (CONFIG_DM9000_BASE + 4) | |
76 | #define CONFIG_NET_RETRY_COUNT 10 | |
77 | ||
78 | #define CONFIG_BOOTP_BOOTFILESIZE | |
2e49984b MV |
79 | #endif |
80 | ||
2e49984b | 81 | #define CONFIG_SYS_DEVICE_NULLDEV 1 |
f9f5486c | 82 | |
2e49984b MV |
83 | /* |
84 | * Clock Configuration | |
85 | */ | |
f9f5486c | 86 | #define CONFIG_SYS_CPUSPEED 0x290 /* 520MHz */ |
2e49984b | 87 | |
2e49984b MV |
88 | /* |
89 | * DRAM Map | |
90 | */ | |
91 | #define CONFIG_NR_DRAM_BANKS 1 /* We have 1 bank of DRAM */ | |
92 | #define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ | |
93 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
94 | ||
95 | #define CONFIG_SYS_DRAM_BASE 0xa0000000 /* CS0 */ | |
96 | #define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB DRAM */ | |
97 | ||
98 | #define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ | |
99 | #define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ | |
100 | ||
f9f5486c | 101 | #define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1 |
6ef6eb91 | 102 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
f9f5486c | 103 | #define CONFIG_SYS_INIT_SP_ADDR 0x5c010000 |
6ef6eb91 | 104 | |
2e49984b MV |
105 | /* |
106 | * NOR FLASH | |
107 | */ | |
108 | #ifdef CONFIG_CMD_FLASH | |
109 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
d817889b | 110 | #define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ |
2e49984b MV |
111 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
112 | ||
113 | #define CONFIG_SYS_FLASH_CFI | |
114 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
d817889b | 115 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT |
2e49984b MV |
116 | |
117 | #define CONFIG_SYS_MAX_FLASH_SECT (4 + 255) | |
118 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
119 | ||
f9f5486c MV |
120 | #define CONFIG_SYS_FLASH_ERASE_TOUT (25 * CONFIG_SYS_HZ) |
121 | #define CONFIG_SYS_FLASH_WRITE_TOUT (25 * CONFIG_SYS_HZ) | |
d817889b MZ |
122 | #define CONFIG_SYS_FLASH_LOCK_TOUT (25 * CONFIG_SYS_HZ) |
123 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (25 * CONFIG_SYS_HZ) | |
2e49984b MV |
124 | |
125 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 | |
126 | #define CONFIG_SYS_FLASH_PROTECTION 1 | |
2e49984b MV |
127 | #endif |
128 | ||
f9f5486c | 129 | #define CONFIG_SYS_MONITOR_BASE 0x0 |
7c49b523 | 130 | #define CONFIG_SYS_MONITOR_LEN 0x40000 |
2e49984b | 131 | |
7c49b523 | 132 | /* Skip factory configuration block */ |
f9f5486c | 133 | #define CONFIG_ENV_ADDR \ |
7c49b523 | 134 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN + 0x40000) |
f9f5486c MV |
135 | #define CONFIG_ENV_SIZE 0x40000 |
136 | #define CONFIG_ENV_SECT_SIZE 0x40000 | |
2e49984b MV |
137 | |
138 | /* | |
139 | * GPIO settings | |
140 | */ | |
141 | #define CONFIG_SYS_GPSR0_VAL 0x00000000 | |
142 | #define CONFIG_SYS_GPSR1_VAL 0x00020000 | |
44ba7a37 | 143 | #define CONFIG_SYS_GPSR2_VAL 0x0002c000 |
2e49984b MV |
144 | #define CONFIG_SYS_GPSR3_VAL 0x00000000 |
145 | ||
146 | #define CONFIG_SYS_GPCR0_VAL 0x00000000 | |
147 | #define CONFIG_SYS_GPCR1_VAL 0x00000000 | |
148 | #define CONFIG_SYS_GPCR2_VAL 0x00000000 | |
149 | #define CONFIG_SYS_GPCR3_VAL 0x00000000 | |
150 | ||
44ba7a37 MZ |
151 | #define CONFIG_SYS_GPDR0_VAL 0xc8008000 |
152 | #define CONFIG_SYS_GPDR1_VAL 0xfc02a981 | |
153 | #define CONFIG_SYS_GPDR2_VAL 0x92c3ffff | |
154 | #define CONFIG_SYS_GPDR3_VAL 0x0061e804 | |
2e49984b | 155 | |
44ba7a37 MZ |
156 | #define CONFIG_SYS_GAFR0_L_VAL 0x80100000 |
157 | #define CONFIG_SYS_GAFR0_U_VAL 0xa5c00010 | |
158 | #define CONFIG_SYS_GAFR1_L_VAL 0x6992901a | |
159 | #define CONFIG_SYS_GAFR1_U_VAL 0xaaa50008 | |
160 | #define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa | |
161 | #define CONFIG_SYS_GAFR2_U_VAL 0x4109a002 | |
162 | #define CONFIG_SYS_GAFR3_L_VAL 0x54000310 | |
163 | #define CONFIG_SYS_GAFR3_U_VAL 0x00005401 | |
2e49984b MV |
164 | |
165 | #define CONFIG_SYS_PSSR_VAL 0x30 | |
166 | ||
167 | /* | |
168 | * Clock settings | |
169 | */ | |
170 | #define CONFIG_SYS_CKEN 0x00500240 | |
171 | #define CONFIG_SYS_CCCR 0x02000290 | |
172 | ||
173 | /* | |
174 | * Memory settings | |
175 | */ | |
44ba7a37 MZ |
176 | #define CONFIG_SYS_MSC0_VAL 0x9ee1c5f2 |
177 | #define CONFIG_SYS_MSC1_VAL 0x9ee1f994 | |
178 | #define CONFIG_SYS_MSC2_VAL 0x9ee19ee1 | |
179 | #define CONFIG_SYS_MDCNFG_VAL 0x090009c9 | |
180 | #define CONFIG_SYS_MDREFR_VAL 0x2003a031 | |
181 | #define CONFIG_SYS_MDMRS_VAL 0x00220022 | |
182 | #define CONFIG_SYS_FLYCNFG_VAL 0x00010001 | |
2e49984b MV |
183 | #define CONFIG_SYS_SXCNFG_VAL 0x40044004 |
184 | ||
185 | /* | |
186 | * PCMCIA and CF Interfaces | |
187 | */ | |
44ba7a37 MZ |
188 | #define CONFIG_SYS_MECR_VAL 0x00000000 |
189 | #define CONFIG_SYS_MCMEM0_VAL 0x00028307 | |
2e49984b | 190 | #define CONFIG_SYS_MCMEM1_VAL 0x00014307 |
44ba7a37 | 191 | #define CONFIG_SYS_MCATT0_VAL 0x00038787 |
2e49984b | 192 | #define CONFIG_SYS_MCATT1_VAL 0x0001c787 |
44ba7a37 | 193 | #define CONFIG_SYS_MCIO0_VAL 0x0002830f |
2e49984b MV |
194 | #define CONFIG_SYS_MCIO1_VAL 0x0001430f |
195 | ||
67a1f00c | 196 | #include "pxa-common.h" |
2e49984b | 197 | |
7c49b523 | 198 | #endif /* __CONFIG_H */ |