[people/ms/u-boot.git] / include / configs / controlcenterd.h

/*
 * (C) Copyright 2013
 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 *
 * based on P1022DS.h
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#endif

/* High Level Configuration Options */
#define CONFIG_BOOKE			/* BOOKE */
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_P1022
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP			/* support multiple processors */

#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_FSL_LAW			/* Use common FSL init code */

#ifdef CONFIG_TRAILBLAZER
#define CONFIG_IDENT_STRING	" controlcenterd trailblazer 0.01"
#else
#define CONFIG_IDENT_STRING	" controlcenterd 0.01"
#endif

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
#endif

#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_CLK_FREQ	66666600
#define CONFIG_DDR_CLK_FREQ	66666600

#define CONFIG_SYS_RAMBOOT

#ifdef CONFIG_TRAILBLAZER

#define CONFIG_SYS_TEXT_BASE		0xf8fc0000
#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

/*
 * Config the L2 Cache
 */
#define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)

#else /* CONFIG_TRAILBLAZER */

#define CONFIG_SYS_TEXT_BASE		0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#endif /* CONFIG_TRAILBLAZER */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

/*
 * Memory map
 *
 * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
 * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
 * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
 *
 * Localbus non-cacheable
 * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
 * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#ifdef CONFIG_TRAILBLAZER
/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
#else
#define CONFIG_SYS_CCSRBAR		0xffe00000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)

/*
 * DDR Setup
 */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM

#define CONFIG_SYS_FSL_DDR3
#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

#define CONFIG_SYS_MEMTEST_START	0x00000000
#define CONFIG_SYS_MEMTEST_END		0x3fffffff

#ifdef CONFIG_TRAILBLAZER
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS 0x52
/*#define CONFIG_FSL_DDR_INTERACTIVE*/
#endif

/*
 * Local Bus Definitions
 */
#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */

#define CONFIG_SYS_ELBC_BASE		0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
#endif

#define CONFIG_UART_BR_PRELIM  \
	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
#define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)

#define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
#define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */

#define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#ifndef CONFIG_TRAILBLAZER
#endif

#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

#ifndef CONFIG_TRAILBLAZER
/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_HARD_SPI

#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		0
#endif

#define CONFIG_SHA1

/*
 * MMC
 */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC

#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR

#ifndef CONFIG_TRAILBLAZER

/*
 * Video
 */
#define CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
#define CONFIG_VIDEO
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_CMD_BMP

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_PCI			/* Enable PCI/PCIE */
#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
#define CONFIG_CMD_PCI

#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */

#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/*
 * SATA
 */
#define CONFIG_LIBATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA

#define CONFIG_FSL_SATA
#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

/*
 * Ethernet
 */
#define CONFIG_TSEC_ENET

#define CONFIG_TSECV2

#define CONFIG_MII			/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */

/*
 * USB
 */
#define CONFIG_USB_EHCI

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

#endif /* CONFIG_TRAILBLAZER */

/*
 * Environment
 */
#if defined(CONFIG_TRAILBLAZER)
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_SYS_MMC_ENV_DEV	0
#endif

#define CONFIG_SYS_EXTRA_ENV_RELOC

#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/*
 * Command line configuration.
 */
#ifndef CONFIG_TRAILBLAZER
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#endif /* CONFIG_TRAILBLAZER */

#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE

#ifndef CONFIG_TRAILBLAZER

#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_REGINFO

/*
 * Board initialisation callbacks
 */
#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT

#else /* CONFIG_TRAILBLAZER */

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT

#endif /* CONFIG_TRAILBLAZER */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_HW_WATCHDOG
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
#define CONFIG_DOS_PARTITION

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TRAILBLAZER

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"mp_holdoff=1\0"

#else

#define CONFIG_HOSTNAME		controlcenterd
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */

#define CONFIG_LOADADDR		1000000


#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
		"protect off $ubootaddr +$filesize && "		\
		"erase $ubootaddr +$filesize && "		\
		"cp.b $loadaddr $ubootaddr $filesize && "	\
		"protect on $ubootaddr +$filesize && "		\
		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
	"consoledev=ttyS1\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=controlcenterd.dtb\0"				\
	"bdev=sda3\0"

/* these are used and NUL-terminated in env_default.h */
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND

#endif /* CONFIG_TRAILBLAZER */

#endif
Commit	Line	Data
b9944a77 DE	1	/*
	2	* (C) Copyright 2013
	3	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
	4	*
	5	* based on P1022DS.h
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
b9944a77 DE	29	#ifdef CONFIG_SDCARD
	30	#define CONFIG_RAMBOOT_SDCARD
	31	#endif
	32
	33	#ifdef CONFIG_SPIFLASH
	34	#define CONFIG_RAMBOOT_SPIFLASH
	35	#endif
	36
	37	/* High Level Configuration Options */
	38	#define CONFIG_BOOKE /* BOOKE */
	39	#define CONFIG_E500 /* BOOKE e500 family */
b9944a77 DE	40	#define CONFIG_P1022
	41	#define CONFIG_CONTROLCENTERD
	42	#define CONFIG_MP /* support multiple processors */
	43
	44	#define CONFIG_SYS_NO_FLASH
	45	#define CONFIG_ENABLE_36BIT_PHYS
	46	#define CONFIG_FSL_LAW /* Use common FSL init code */
	47
	48	#ifdef CONFIG_TRAILBLAZER
	49	#define CONFIG_IDENT_STRING " controlcenterd trailblazer 0.01"
	50	#else
	51	#define CONFIG_IDENT_STRING " controlcenterd 0.01"
	52	#endif
	53
	54	#ifdef CONFIG_PHYS_64BIT
	55	#define CONFIG_ADDR_MAP
	56	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	57	#endif
	58
	59	#define CONFIG_L2_CACHE
	60	#define CONFIG_BTB
	61
	62	#define CONFIG_SYS_CLK_FREQ 66666600
	63	#define CONFIG_DDR_CLK_FREQ 66666600
	64
	65	#define CONFIG_SYS_RAMBOOT
	66
	67	#ifdef CONFIG_TRAILBLAZER
	68
	69	#define CONFIG_SYS_TEXT_BASE 0xf8fc0000
	70	#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
	71	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	72
	73	/*
	74	* Config the L2 Cache
	75	*/
	76	#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
	77	#ifdef CONFIG_PHYS_64BIT
	78	#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
	79	#else
	80	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	81	#endif
	82	#define CONFIG_SYS_L2_SIZE (256 << 10)
	83	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	84
	85	#else /* CONFIG_TRAILBLAZER */
	86
	87	#define CONFIG_SYS_TEXT_BASE 0x11000000
	88	#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
	89	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	90
	91	#endif /* CONFIG_TRAILBLAZER */
	92
	93	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	94	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	95
b9944a77 DE	96	/*
	97	* Memory map
	98	*
	99	* 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
	100	* 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
	101	* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
	102	*
	103	* Localbus non-cacheable
	104	* 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
	105	* 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
	106	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
	107	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	108	*/
	109
	110	#define CONFIG_SYS_INIT_RAM_LOCK
	111	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
	112	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
	113	#define CONFIG_SYS_GBL_DATA_OFFSET \
	114	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	115	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	116
	117	#ifdef CONFIG_TRAILBLAZER
	118	/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
	119	#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
	120	#else
	121	#define CONFIG_SYS_CCSRBAR 0xffe00000
	122	#endif
	123	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	124	#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
	125
	126	/*
	127	* DDR Setup
	128	*/
	129
	130	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	131	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	132	#define CONFIG_SYS_SDRAM_SIZE 1024
	133	#define CONFIG_VERY_BIG_RAM
	134
5614e71b	135	#define CONFIG_SYS_FSL_DDR3
b9944a77 DE	136	#define CONFIG_NUM_DDR_CONTROLLERS 1
	137	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	138	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	139
	140	#define CONFIG_SYS_MEMTEST_START 0x00000000
	141	#define CONFIG_SYS_MEMTEST_END 0x3fffffff
	142
	143	#ifdef CONFIG_TRAILBLAZER
	144	#define CONFIG_SPD_EEPROM
	145	#define SPD_EEPROM_ADDRESS 0x52
	146	/#define CONFIG_FSL_DDR_INTERACTIVE/
	147	#endif
	148
	149	/*
	150	* Local Bus Definitions
	151	*/
	152	#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
	153
	154	#define CONFIG_SYS_ELBC_BASE 0xe0000000
	155	#ifdef CONFIG_PHYS_64BIT
	156	#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
	157	#else
	158	#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
	159	#endif
	160
	161	#define CONFIG_UART_BR_PRELIM \
	162	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) \| BR_PS_8 \| BR_V)
	163	#define CONFIG_UART_OR_PRELIM (OR_AM_32KB \| 0xff7)
	164
	165	#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
	166	#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
	167
	168	#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
	169	#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
	170
	171	/*
	172	* Serial Port
	173	*/
	174	#define CONFIG_CONS_INDEX 2
b9944a77 DE	175	#define CONFIG_SYS_NS16550_SERIAL
	176	#define CONFIG_SYS_NS16550_REG_SIZE 1
	177	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	178
	179	#define CONFIG_SYS_BAUDRATE_TABLE \
	180	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	181
	182	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	183	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	184
	185	/*
	186	* I2C
	187	*/
00f792e0 HS	188	#define CONFIG_SYS_I2C
	189	#define CONFIG_SYS_I2C_FSL
	190	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	191	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	192	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	193	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	194	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	195	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
5568fb44 DE	196
5568fb44 DE	197	#ifndef CONFIG_TRAILBLAZER
5568fb44	198	#endif
b9944a77 DE	199
	200	#define CONFIG_PCA9698 /* NXP PCA9698 */
	201
	202	#define CONFIG_CMD_EEPROM
	203	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	204	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	205
	206	#ifndef CONFIG_TRAILBLAZER
	207	/*
	208	* eSPI - Enhanced SPI
	209	*/
	210	#define CONFIG_HARD_SPI
b9944a77	211
b9944a77 DE	212	#define CONFIG_SF_DEFAULT_SPEED 10000000
	213	#define CONFIG_SF_DEFAULT_MODE 0
	214	#endif
	215
b9944a77	216	#define CONFIG_SHA1
b9944a77 DE	217
	218	/*
	219	* MMC
	220	*/
	221	#define CONFIG_MMC
	222	#define CONFIG_GENERIC_MMC
b9944a77 DE	223
	224	#define CONFIG_FSL_ESDHC
	225	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
	226
b9944a77 DE	227	#ifndef CONFIG_TRAILBLAZER
	228
	229	/*
	230	* Video
	231	*/
	232	#define CONFIG_FSL_DIU_FB
	233	#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
	234	#define CONFIG_VIDEO
	235	#define CONFIG_CFB_CONSOLE
	236	#define CONFIG_VGA_AS_SINGLE_DEVICE
	237	#define CONFIG_CMD_BMP
	238
	239	/*
	240	* General PCI
	241	* Memory space is mapped 1-1, but I/O space must start from 0.
	242	*/
	243	#define CONFIG_PCI /* Enable PCI/PCIE */
b38eaec5	244	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b9944a77 DE	245	#define CONFIG_PCI_INDIRECT_BRIDGE
	246	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	247	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	248	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	249	#define CONFIG_CMD_PCI
	250
	251	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	252	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	253
	254	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
	255	#ifdef CONFIG_PHYS_64BIT
	256	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
	257	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
	258	#else
	259	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	260	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	261	#endif
	262	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	263	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	264	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	265	#ifdef CONFIG_PHYS_64BIT
	266	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
	267	#else
	268	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	269	#endif
	270	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	271
	272	/*
	273	* SATA
	274	*/
	275	#define CONFIG_LIBATA
	276	#define CONFIG_LBA48
	277	#define CONFIG_CMD_SATA
	278
	279	#define CONFIG_FSL_SATA
	280	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	281	#define CONFIG_SATA1
	282	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	283	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	284	#define CONFIG_SATA2
	285	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	286	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	287
	288	/*
	289	* Ethernet
	290	*/
	291	#define CONFIG_TSEC_ENET
	292
	293	#define CONFIG_TSECV2
	294
	295	#define CONFIG_MII /* MII PHY management */
	296	#define CONFIG_TSEC1 1
	297	#define CONFIG_TSEC1_NAME "eTSEC1"
	298	#define CONFIG_TSEC2 1
	299	#define CONFIG_TSEC2_NAME "eTSEC2"
	300
	301	#define TSEC1_PHY_ADDR 0
	302	#define TSEC2_PHY_ADDR 1
	303
	304	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	305	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	306
	307	#define TSEC1_PHYIDX 0
	308	#define TSEC2_PHYIDX 0
309
310	#define CONFIG_ETHPRIME "eTSEC1"
311
312	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
313
314	/*
315	* USB
316	*/
317	#define CONFIG_USB_EHCI
b9944a77 DE	318
	319	#define CONFIG_HAS_FSL_DR_USB
	320	#define CONFIG_USB_EHCI_FSL
	321	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	322
	323	#endif /* CONFIG_TRAILBLAZER */
	324
	325	/*
	326	* Environment
	327	*/
	328	#if defined(CONFIG_TRAILBLAZER)
	329	#define CONFIG_ENV_IS_NOWHERE
	330	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
b9944a77 DE	331	#elif defined(CONFIG_RAMBOOT_SPIFLASH)
	332	#define CONFIG_ENV_IS_IN_SPI_FLASH
	333	#define CONFIG_ENV_SPI_BUS 0
	334	#define CONFIG_ENV_SPI_CS 0
	335	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	336	#define CONFIG_ENV_SPI_MODE 0
	337	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	338	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	339	#define CONFIG_ENV_SECT_SIZE 0x10000
	340	#elif defined(CONFIG_RAMBOOT_SDCARD)
	341	#define CONFIG_ENV_IS_IN_MMC
	342	#define CONFIG_FSL_FIXED_MMC_LOCATION
	343	#define CONFIG_ENV_SIZE 0x2000
	344	#define CONFIG_SYS_MMC_ENV_DEV 0
	345	#endif
	346
	347	#define CONFIG_SYS_EXTRA_ENV_RELOC
	348
	349	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	350
	351	/*
	352	* Command line configuration.
	353	*/
	354	#ifndef CONFIG_TRAILBLAZER
b9944a77 DE	355	#define CONFIG_SYS_LONGHELP
	356	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
	357	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
	358	#endif /* CONFIG_TRAILBLAZER */
	359
	360	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
b9944a77 DE	361	#ifdef CONFIG_CMD_KGDB
	362	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	363	#else
	364	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	365	#endif
	366	/* Print Buffer Size */
	367	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	368	#define CONFIG_SYS_MAXARGS 16
	369	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	370
b9944a77 DE	371	#ifndef CONFIG_TRAILBLAZER
b9944a77 DE	372
b9944a77	373	#define CONFIG_CMD_ERRATA
b9944a77	374	#define CONFIG_CMD_IRQ
b9944a77 DE	375	#define CONFIG_CMD_REGINFO
	376
	377	/*
	378	* Board initialisation callbacks
	379	*/
	380	#define CONFIG_BOARD_EARLY_INIT_F
	381	#define CONFIG_BOARD_EARLY_INIT_R
	382	#define CONFIG_MISC_INIT_R
	383	#define CONFIG_LAST_STAGE_INIT
	384
b9944a77 DE	385	#else /* CONFIG_TRAILBLAZER */
	386
	387	#define CONFIG_BOARD_EARLY_INIT_F
	388	#define CONFIG_BOARD_EARLY_INIT_R
	389	#define CONFIG_LAST_STAGE_INIT
b9944a77 DE	390
	391	#endif /* CONFIG_TRAILBLAZER */
	392
	393	/*
	394	* Miscellaneous configurable options
	395	*/
b9944a77 DE	396	#define CONFIG_HW_WATCHDOG
	397	#define CONFIG_LOADS_ECHO
	398	#define CONFIG_SYS_LOADS_BAUD_CHANGE
	399	#define CONFIG_DOS_PARTITION
	400
	401	/*
	402	* For booting Linux, the board info and command line data
	403	* have to be in the first 64 MB of memory, since this is
	404	* the maximum mapped by the Linux kernel during initialization.
	405	*/
	406	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
	407	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	408
	409	/*
	410	* Environment Configuration
	411	*/
	412
	413	#ifdef CONFIG_TRAILBLAZER
	414
b9944a77 DE	415	#define CONFIG_BAUDRATE 115200
	416
	417	#define CONFIG_EXTRA_ENV_SETTINGS \
	418	"mp_holdoff=1\0"
	419
	420	#else
	421
	422	#define CONFIG_HOSTNAME controlcenterd
	423	#define CONFIG_ROOTPATH "/opt/nfsroot"
	424	#define CONFIG_BOOTFILE "uImage"
	425	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
	426
	427	#define CONFIG_LOADADDR 1000000
	428
b9944a77 DE	429
	430	#define CONFIG_BAUDRATE 115200
	431
	432	#define CONFIG_EXTRA_ENV_SETTINGS \
	433	"netdev=eth0\0" \
	434	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	435	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	436	"tftpflash=tftpboot $loadaddr $uboot && " \
	437	"protect off $ubootaddr +$filesize && " \
	438	"erase $ubootaddr +$filesize && " \
	439	"cp.b $loadaddr $ubootaddr $filesize && " \
	440	"protect on $ubootaddr +$filesize && " \
	441	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	442	"consoledev=ttyS1\0" \
	443	"ramdiskaddr=2000000\0" \
	444	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	445	"fdtaddr=1e00000\0" \
b9944a77 DE	446	"fdtfile=controlcenterd.dtb\0" \
	447	"bdev=sda3\0"
	448
	449	/* these are used and NUL-terminated in env_default.h */
	450	#define CONFIG_NFSBOOTCOMMAND \
	451	"setenv bootargs root=/dev/nfs rw " \
	452	"nfsroot=$serverip:$rootpath " \
	453	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	454	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	455	"tftp $loadaddr $bootfile;" \
	456	"tftp $fdtaddr $fdtfile;" \
	457	"bootm $loadaddr - $fdtaddr"
	458
	459	#define CONFIG_RAMBOOTCOMMAND \
	460	"setenv bootargs root=/dev/ram rw " \
	461	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	462	"tftp $ramdiskaddr $ramdiskfile;" \
	463	"tftp $loadaddr $bootfile;" \
	464	"tftp $fdtaddr $fdtfile;" \
	465	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	466
	467	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	468
	469	#endif /* CONFIG_TRAILBLAZER */
	470
	471	#endif