[people/ms/u-boot.git] / include / configs / controlcenterd.h

/*
 * (C) Copyright 2013
 * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
 *
 * based on P1022DS.h
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#endif

#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#endif

/* High Level Configuration Options */
#define CONFIG_CONTROLCENTERD
#define CONFIG_MP			/* support multiple processors */

#define CONFIG_ENABLE_36BIT_PHYS

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
#endif

#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_CLK_FREQ	66666600
#define CONFIG_DDR_CLK_FREQ	66666600

#define CONFIG_SYS_RAMBOOT

#ifdef CONFIG_TRAILBLAZER

#define CONFIG_RESET_VECTOR_ADDRESS	0xf8fffffc
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)

/*
 * Config the L2 Cache
 */
#define CONFIG_SYS_INIT_L2_ADDR		0xf8fc0000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	0xff8fc0000ull
#else
#define CONFIG_SYS_INIT_L2_ADDR_PHYS	CONFIG_SYS_INIT_L2_ADDR
#endif
#define CONFIG_SYS_L2_SIZE		(256 << 10)
#define CONFIG_SYS_INIT_L2_END	(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)

#else /* CONFIG_TRAILBLAZER */

#define CONFIG_RESET_VECTOR_ADDRESS	0x1107fffc
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)

#endif /* CONFIG_TRAILBLAZER */

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_MALLOC_LEN		(10 * 1024 * 1024)

/*
 * Memory map
 *
 * 0x0000_0000	0x3fff_ffff	DDR			1G Cacheable
 * 0xc000_0000	0xdfff_ffff	PCI Express Mem		512M non-cacheable
 * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
 *
 * Localbus non-cacheable
 * 0xe000_0000	0xe00f_ffff	eLBC			1M non-cacheable
 * 0xf8fc0000	0xf8ff_ffff	L2 SRAM			256k Cacheable
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 */

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x00004000 /* used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#ifdef CONFIG_TRAILBLAZER
/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
#define CONFIG_SYS_CCSRBAR		CONFIG_SYS_CCSRBAR_DEFAULT
#else
#define CONFIG_SYS_CCSRBAR		0xffe00000
#endif
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
#define CONFIG_SYS_MPC85xx_GPIO3_ADDR	(CONFIG_SYS_CCSRBAR+0xf200)

/*
 * DDR Setup
 */

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_SYS_SDRAM_SIZE 1024
#define CONFIG_VERY_BIG_RAM

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

#define CONFIG_SYS_MEMTEST_START	0x00000000
#define CONFIG_SYS_MEMTEST_END		0x3fffffff

#ifdef CONFIG_TRAILBLAZER
#define CONFIG_SPD_EEPROM
#define SPD_EEPROM_ADDRESS 0x52
/*#define CONFIG_FSL_DDR_INTERACTIVE*/
#endif

/*
 * Local Bus Definitions
 */

#define CONFIG_SYS_ELBC_BASE		0xe0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_ELBC_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_ELBC_BASE_PHYS	CONFIG_SYS_ELBC_BASE
#endif

#define CONFIG_UART_BR_PRELIM  \
	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
#define CONFIG_UART_OR_PRELIM	(OR_AM_32KB | 0xff7)

#define CONFIG_SYS_BR0_PRELIM	0 /* CS0 was originally intended for FPGA */
#define CONFIG_SYS_OR0_PRELIM	0 /* debugging, was never used */

#define CONFIG_SYS_BR1_PRELIM	CONFIG_UART_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM	CONFIG_UART_OR_PRELIM

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_FSL_I2C2_SPEED	400000
#define CONFIG_SYS_FSL_I2C2_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C2_OFFSET	0x3100

#ifndef CONFIG_TRAILBLAZER
#endif

#define CONFIG_PCA9698			/* NXP PCA9698 */

#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

#ifndef CONFIG_TRAILBLAZER
/*
 * eSPI - Enhanced SPI
 */
#define CONFIG_HARD_SPI

#define CONFIG_SF_DEFAULT_SPEED		10000000
#define CONFIG_SF_DEFAULT_MODE		0
#endif

/*
 * MMC
 */
#define CONFIG_FSL_ESDHC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR

#ifndef CONFIG_TRAILBLAZER

/*
 * Video
 */
#define CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_PCIE1			/* PCIE controller 1 (slot 1) */
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */

#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/*
 * SATA
 */
#define CONFIG_LBA48

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

/*
 * Ethernet
 */
#define CONFIG_TSEC_ENET

#define CONFIG_TSECV2

#define CONFIG_MII			/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

/*
 * USB
 */

#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET

#endif /* CONFIG_TRAILBLAZER */

/*
 * Environment
 */
#if defined(CONFIG_TRAILBLAZER)
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#elif defined(CONFIG_RAMBOOT_SPIFLASH)
#define CONFIG_ENV_SPI_BUS	0
#define CONFIG_ENV_SPI_CS	0
#define CONFIG_ENV_SPI_MAX_HZ	10000000
#define CONFIG_ENV_SPI_MODE	0
#define CONFIG_ENV_SIZE		0x2000		/* 8KB */
#define CONFIG_ENV_OFFSET	0x100000	/* 1MB */
#define CONFIG_ENV_SECT_SIZE	0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_FSL_FIXED_MMC_LOCATION
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_SYS_MMC_ENV_DEV	0
#endif

#define CONFIG_SYS_EXTRA_ENV_RELOC

/*
 * Command line configuration.
 */

#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#ifndef CONFIG_TRAILBLAZER
/*
 * Board initialisation callbacks
 */
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_LAST_STAGE_INIT

#else /* CONFIG_TRAILBLAZER */

#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_LAST_STAGE_INIT

#endif /* CONFIG_TRAILBLAZER */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_HW_WATCHDOG
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Linux Memory map */
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Environment Configuration
 */

#ifdef CONFIG_TRAILBLAZER
#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"mp_holdoff=1\0"

#else

#define CONFIG_HOSTNAME		controlcenterd
#define CONFIG_ROOTPATH		"/opt/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP */

#define CONFIG_LOADADDR		1000000

#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"netdev=eth0\0"						\
	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"		\
	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"	\
	"tftpflash=tftpboot $loadaddr $uboot && "		\
		"protect off $ubootaddr +$filesize && "		\
		"erase $ubootaddr +$filesize && "		\
		"cp.b $loadaddr $ubootaddr $filesize && "	\
		"protect on $ubootaddr +$filesize && "		\
		"cmp.b $loadaddr $ubootaddr $filesize\0"	\
	"consoledev=ttyS1\0"					\
	"ramdiskaddr=2000000\0"					\
	"ramdiskfile=rootfs.ext2.gz.uboot\0"			\
	"fdtaddr=1e00000\0"					\
	"fdtfile=controlcenterd.dtb\0"				\
	"bdev=sda3\0"

/* these are used and NUL-terminated in env_default.h */
#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
	"console=$consoledev,$baudrate $othbootargs $videobootargs;"	\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND

#endif /* CONFIG_TRAILBLAZER */

#endif
Commit	Line	Data
b9944a77 DE	1	/*
	2	* (C) Copyright 2013
	3	* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
	4	*
	5	* based on P1022DS.h
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
b9944a77 DE	29	#ifdef CONFIG_SDCARD
	30	#define CONFIG_RAMBOOT_SDCARD
	31	#endif
	32
	33	#ifdef CONFIG_SPIFLASH
	34	#define CONFIG_RAMBOOT_SPIFLASH
	35	#endif
	36
	37	/* High Level Configuration Options */
b9944a77 DE	38	#define CONFIG_CONTROLCENTERD
	39	#define CONFIG_MP /* support multiple processors */
	40
b9944a77	41	#define CONFIG_ENABLE_36BIT_PHYS
b9944a77	42
b9944a77 DE	43	#ifdef CONFIG_PHYS_64BIT
	44	#define CONFIG_ADDR_MAP
	45	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
	46	#endif
	47
	48	#define CONFIG_L2_CACHE
	49	#define CONFIG_BTB
	50
	51	#define CONFIG_SYS_CLK_FREQ 66666600
	52	#define CONFIG_DDR_CLK_FREQ 66666600
	53
	54	#define CONFIG_SYS_RAMBOOT
	55
	56	#ifdef CONFIG_TRAILBLAZER
	57
b9944a77 DE	58	#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
	59	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	60
	61	/*
	62	* Config the L2 Cache
	63	*/
	64	#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
	65	#ifdef CONFIG_PHYS_64BIT
	66	#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
	67	#else
	68	#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
	69	#endif
	70	#define CONFIG_SYS_L2_SIZE (256 << 10)
	71	#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
	72
	73	#else /* CONFIG_TRAILBLAZER */
	74
b9944a77 DE	75	#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
	76	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	77
	78	#endif /* CONFIG_TRAILBLAZER */
	79
	80	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
	81	#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
	82
b9944a77 DE	83	/*
	84	* Memory map
	85	*
	86	* 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
	87	* 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
	88	* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
	89	*
	90	* Localbus non-cacheable
	91	* 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
	92	* 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
	93	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
	94	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	95	*/
	96
	97	#define CONFIG_SYS_INIT_RAM_LOCK
	98	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
	99	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
	100	#define CONFIG_SYS_GBL_DATA_OFFSET \
	101	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	102	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	103
	104	#ifdef CONFIG_TRAILBLAZER
	105	/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
	106	#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
	107	#else
	108	#define CONFIG_SYS_CCSRBAR 0xffe00000
	109	#endif
	110	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
	111	#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
	112
	113	/*
	114	* DDR Setup
	115	*/
	116
	117	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	118	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	119	#define CONFIG_SYS_SDRAM_SIZE 1024
	120	#define CONFIG_VERY_BIG_RAM
	121
b9944a77 DE	122	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	123	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	124
	125	#define CONFIG_SYS_MEMTEST_START 0x00000000
	126	#define CONFIG_SYS_MEMTEST_END 0x3fffffff
	127
	128	#ifdef CONFIG_TRAILBLAZER
	129	#define CONFIG_SPD_EEPROM
	130	#define SPD_EEPROM_ADDRESS 0x52
	131	/#define CONFIG_FSL_DDR_INTERACTIVE/
	132	#endif
	133
	134	/*
	135	* Local Bus Definitions
	136	*/
b9944a77 DE	137
	138	#define CONFIG_SYS_ELBC_BASE 0xe0000000
	139	#ifdef CONFIG_PHYS_64BIT
	140	#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
	141	#else
	142	#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
	143	#endif
	144
	145	#define CONFIG_UART_BR_PRELIM \
	146	(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) \| BR_PS_8 \| BR_V)
	147	#define CONFIG_UART_OR_PRELIM (OR_AM_32KB \| 0xff7)
	148
	149	#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
	150	#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
	151
	152	#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
	153	#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
	154
	155	/*
	156	* Serial Port
	157	*/
	158	#define CONFIG_CONS_INDEX 2
b9944a77 DE	159	#define CONFIG_SYS_NS16550_SERIAL
	160	#define CONFIG_SYS_NS16550_REG_SIZE 1
	161	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	162
	163	#define CONFIG_SYS_BAUDRATE_TABLE \
	164	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	165
	166	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	167	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	168
	169	/*
	170	* I2C
	171	*/
00f792e0 HS	172	#define CONFIG_SYS_I2C
	173	#define CONFIG_SYS_I2C_FSL
	174	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	175	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	176	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	177	#define CONFIG_SYS_FSL_I2C2_SPEED 400000
	178	#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
	179	#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
5568fb44 DE	180
5568fb44 DE	181	#ifndef CONFIG_TRAILBLAZER
5568fb44	182	#endif
b9944a77 DE	183
	184	#define CONFIG_PCA9698 /* NXP PCA9698 */
	185
b9944a77 DE	186	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
	187	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	188
	189	#ifndef CONFIG_TRAILBLAZER
	190	/*
	191	* eSPI - Enhanced SPI
	192	*/
	193	#define CONFIG_HARD_SPI
b9944a77	194
b9944a77 DE	195	#define CONFIG_SF_DEFAULT_SPEED 10000000
	196	#define CONFIG_SF_DEFAULT_MODE 0
	197	#endif
	198
b9944a77 DE	199	/*
	200	* MMC
	201	*/
b9944a77 DE	202	#define CONFIG_FSL_ESDHC
	203	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
	204
b9944a77 DE	205	#ifndef CONFIG_TRAILBLAZER
	206
	207	/*
	208	* Video
	209	*/
	210	#define CONFIG_FSL_DIU_FB
	211	#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
b9944a77 DE	212
	213	/*
	214	* General PCI
	215	* Memory space is mapped 1-1, but I/O space must start from 0.
	216	*/
b38eaec5	217	#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
b9944a77	218	#define CONFIG_PCI_INDIRECT_BRIDGE
b9944a77 DE	219	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
b9944a77 DE	220	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
b9944a77 DE	221
	222	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	223	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	224
	225	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
	226	#ifdef CONFIG_PHYS_64BIT
	227	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
	228	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
	229	#else
	230	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	231	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	232	#endif
	233	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	234	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	235	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
	236	#ifdef CONFIG_PHYS_64BIT
	237	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
	238	#else
	239	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	240	#endif
	241	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	242
	243	/*
	244	* SATA
	245	*/
b9944a77	246	#define CONFIG_LBA48
b9944a77	247
b9944a77 DE	248	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	249	#define CONFIG_SATA1
	250	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	251	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	252	#define CONFIG_SATA2
	253	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	254	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	255
	256	/*
	257	* Ethernet
	258	*/
	259	#define CONFIG_TSEC_ENET
	260
	261	#define CONFIG_TSECV2
	262
	263	#define CONFIG_MII /* MII PHY management */
	264	#define CONFIG_TSEC1 1
	265	#define CONFIG_TSEC1_NAME "eTSEC1"
	266	#define CONFIG_TSEC2 1
	267	#define CONFIG_TSEC2_NAME "eTSEC2"
	268
	269	#define TSEC1_PHY_ADDR 0
	270	#define TSEC2_PHY_ADDR 1
	271
	272	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	273	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	274
	275	#define TSEC1_PHYIDX 0
	276	#define TSEC2_PHYIDX 0
	277
	278	#define CONFIG_ETHPRIME "eTSEC1"
	279
b9944a77 DE	280	/*
	281	* USB
	282	*/
b9944a77 DE	283
	284	#define CONFIG_HAS_FSL_DR_USB
	285	#define CONFIG_USB_EHCI_FSL
	286	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	287
	288	#endif /* CONFIG_TRAILBLAZER */
	289
	290	/*
	291	* Environment
	292	*/
	293	#if defined(CONFIG_TRAILBLAZER)
b9944a77	294	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
b9944a77	295	#elif defined(CONFIG_RAMBOOT_SPIFLASH)
b9944a77 DE	296	#define CONFIG_ENV_SPI_BUS 0
	297	#define CONFIG_ENV_SPI_CS 0
	298	#define CONFIG_ENV_SPI_MAX_HZ 10000000
	299	#define CONFIG_ENV_SPI_MODE 0
	300	#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
	301	#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
	302	#define CONFIG_ENV_SECT_SIZE 0x10000
	303	#elif defined(CONFIG_RAMBOOT_SDCARD)
b9944a77 DE	304	#define CONFIG_FSL_FIXED_MMC_LOCATION
	305	#define CONFIG_ENV_SIZE 0x2000
	306	#define CONFIG_SYS_MMC_ENV_DEV 0
	307	#endif
	308
	309	#define CONFIG_SYS_EXTRA_ENV_RELOC
	310
b9944a77 DE	311	/*
	312	* Command line configuration.
	313	*/
b9944a77 DE	314
b9944a77 DE	315	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
b9944a77	316
b9944a77	317	#ifndef CONFIG_TRAILBLAZER
b9944a77 DE	318	/*
	319	* Board initialisation callbacks
	320	*/
b9944a77 DE	321	#define CONFIG_BOARD_EARLY_INIT_R
	322	#define CONFIG_MISC_INIT_R
	323	#define CONFIG_LAST_STAGE_INIT
	324
b9944a77 DE	325	#else /* CONFIG_TRAILBLAZER */
b9944a77 DE	326
b9944a77 DE	327	#define CONFIG_BOARD_EARLY_INIT_R
b9944a77 DE	328	#define CONFIG_LAST_STAGE_INIT
b9944a77 DE	329
	330	#endif /* CONFIG_TRAILBLAZER */
	331
	332	/*
	333	* Miscellaneous configurable options
	334	*/
b9944a77 DE	335	#define CONFIG_HW_WATCHDOG
	336	#define CONFIG_LOADS_ECHO
	337	#define CONFIG_SYS_LOADS_BAUD_CHANGE
b9944a77 DE	338
	339	/*
	340	* For booting Linux, the board info and command line data
	341	* have to be in the first 64 MB of memory, since this is
	342	* the maximum mapped by the Linux kernel during initialization.
	343	*/
	344	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
	345	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
	346
	347	/*
	348	* Environment Configuration
	349	*/
	350
	351	#ifdef CONFIG_TRAILBLAZER
b9944a77 DE	352	#define CONFIG_EXTRA_ENV_SETTINGS \
	353	"mp_holdoff=1\0"
	354
	355	#else
	356
	357	#define CONFIG_HOSTNAME controlcenterd
	358	#define CONFIG_ROOTPATH "/opt/nfsroot"
	359	#define CONFIG_BOOTFILE "uImage"
	360	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
	361
	362	#define CONFIG_LOADADDR 1000000
	363
b9944a77 DE	364	#define CONFIG_EXTRA_ENV_SETTINGS \
	365	"netdev=eth0\0" \
	366	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
	367	"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
	368	"tftpflash=tftpboot $loadaddr $uboot && " \
	369	"protect off $ubootaddr +$filesize && " \
	370	"erase $ubootaddr +$filesize && " \
	371	"cp.b $loadaddr $ubootaddr $filesize && " \
	372	"protect on $ubootaddr +$filesize && " \
	373	"cmp.b $loadaddr $ubootaddr $filesize\0" \
	374	"consoledev=ttyS1\0" \
	375	"ramdiskaddr=2000000\0" \
	376	"ramdiskfile=rootfs.ext2.gz.uboot\0" \
b24a4f62	377	"fdtaddr=1e00000\0" \
b9944a77 DE	378	"fdtfile=controlcenterd.dtb\0" \
	379	"bdev=sda3\0"
	380
	381	/* these are used and NUL-terminated in env_default.h */
	382	#define CONFIG_NFSBOOTCOMMAND \
	383	"setenv bootargs root=/dev/nfs rw " \
	384	"nfsroot=$serverip:$rootpath " \
	385	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	386	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	387	"tftp $loadaddr $bootfile;" \
	388	"tftp $fdtaddr $fdtfile;" \
	389	"bootm $loadaddr - $fdtaddr"
	390
	391	#define CONFIG_RAMBOOTCOMMAND \
	392	"setenv bootargs root=/dev/ram rw " \
	393	"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
	394	"tftp $ramdiskaddr $ramdiskfile;" \
	395	"tftp $loadaddr $bootfile;" \
	396	"tftp $fdtaddr $fdtfile;" \
	397	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	398
	399	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	400
	401	#endif /* CONFIG_TRAILBLAZER */
	402
	403	#endif