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d1712369 | 1 | /* |
a09b9b68 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
d1712369 KG |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * Corenet DS style board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | #include "../board/freescale/common/ics307_clk.h" | |
30 | ||
2a9fab82 SX |
31 | #ifdef CONFIG_RAMBOOT_PBL |
32 | #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE | |
33 | #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc | |
34 | #endif | |
35 | ||
d1712369 KG |
36 | /* High Level Configuration Options */ |
37 | #define CONFIG_BOOKE | |
38 | #define CONFIG_E500 /* BOOKE e500 family */ | |
39 | #define CONFIG_E500MC /* BOOKE e500mc family */ | |
40 | #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ | |
41 | #define CONFIG_MPC85xx /* MPC85xx/PQ3 platform */ | |
42 | #define CONFIG_FSL_CORENET /* Freescale CoreNet platform */ | |
43 | #define CONFIG_MP /* support multiple processors */ | |
44 | ||
ed179152 KG |
45 | #ifndef CONFIG_SYS_TEXT_BASE |
46 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
47 | #endif | |
48 | ||
7a577fda KG |
49 | #ifndef CONFIG_RESET_VECTOR_ADDRESS |
50 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
51 | #endif | |
52 | ||
d1712369 KG |
53 | #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ |
54 | #define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS | |
55 | #define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ | |
56 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
57 | #define CONFIG_PCIE1 /* PCIE controler 1 */ | |
58 | #define CONFIG_PCIE2 /* PCIE controler 2 */ | |
59 | #define CONFIG_PCIE3 /* PCIE controler 3 */ | |
60 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
61 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
d1712369 | 62 | |
a09b9b68 | 63 | #define CONFIG_SYS_SRIO |
d1712369 KG |
64 | #define CONFIG_SRIO1 /* SRIO port 1 */ |
65 | #define CONFIG_SRIO2 /* SRIO port 2 */ | |
66 | ||
67 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
68 | ||
69 | #define CONFIG_ENV_OVERWRITE | |
70 | ||
2a9fab82 SX |
71 | #if defined(CONFIG_RAMBOOT_PBL) |
72 | #define CONFIG_SYS_NO_FLASH /* Store ENV in memory only */ | |
73 | #endif | |
74 | ||
d1712369 KG |
75 | #ifdef CONFIG_SYS_NO_FLASH |
76 | #define CONFIG_ENV_IS_NOWHERE | |
77 | #else | |
78 | #define CONFIG_ENV_IS_IN_FLASH | |
79 | #define CONFIG_FLASH_CFI_DRIVER | |
80 | #define CONFIG_SYS_FLASH_CFI | |
2a9fab82 | 81 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
d1712369 KG |
82 | #endif |
83 | ||
84 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ | |
d1712369 KG |
85 | |
86 | /* | |
87 | * These can be toggled for performance analysis, otherwise use default. | |
88 | */ | |
89 | #define CONFIG_SYS_CACHE_STASHING | |
90 | #define CONFIG_BACKSIDE_L2_CACHE | |
91 | #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E | |
92 | #define CONFIG_BTB /* toggle branch predition */ | |
8ed20f2c | 93 | #define CONFIG_DDR_ECC |
d1712369 KG |
94 | #ifdef CONFIG_DDR_ECC |
95 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
96 | #define CONFIG_MEM_INIT_VALUE 0xdeadbeef | |
97 | #endif | |
98 | ||
99 | #define CONFIG_ENABLE_36BIT_PHYS | |
100 | ||
101 | #ifdef CONFIG_PHYS_64BIT | |
102 | #define CONFIG_ADDR_MAP | |
103 | #define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */ | |
104 | #endif | |
105 | ||
4672e1ea | 106 | #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ |
d1712369 KG |
107 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
108 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
109 | #define CONFIG_SYS_ALT_MEMTEST | |
110 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
111 | ||
2a9fab82 SX |
112 | /* |
113 | * Config the L3 Cache as L3 SRAM | |
114 | */ | |
115 | #define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE | |
116 | #ifdef CONFIG_PHYS_64BIT | |
117 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS (0xf00000000ull | CONFIG_RAMBOOT_TEXT_BASE) | |
118 | #else | |
119 | #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR | |
120 | #endif | |
121 | #define CONFIG_SYS_L3_SIZE (1024 << 10) | |
122 | #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) | |
123 | ||
d1712369 KG |
124 | /* |
125 | * Base addresses -- Note these are effective addresses where the | |
126 | * actual resources get mapped (not physical addresses) | |
127 | */ | |
128 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000 /* CCSRBAR Default */ | |
129 | #define CONFIG_SYS_CCSRBAR 0xfe000000 /* relocated CCSRBAR */ | |
130 | #ifdef CONFIG_PHYS_64BIT | |
131 | #define CONFIG_SYS_CCSRBAR_PHYS 0xffe000000ull /* physical addr of CCSRBAR */ | |
132 | #else | |
133 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
134 | #endif | |
135 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
136 | ||
137 | #ifdef CONFIG_PHYS_64BIT | |
138 | #define CONFIG_SYS_DCSRBAR 0xf0000000 | |
139 | #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull | |
140 | #endif | |
141 | ||
142 | /* EEPROM */ | |
143 | #define CONFIG_ID_EEPROM | |
144 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
145 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
146 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
147 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
148 | ||
149 | /* | |
150 | * DDR Setup | |
151 | */ | |
152 | #define CONFIG_VERY_BIG_RAM | |
153 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
154 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
155 | ||
156 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
90870d98 | 157 | #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) |
d1712369 KG |
158 | |
159 | #define CONFIG_DDR_SPD | |
160 | #define CONFIG_FSL_DDR3 | |
161 | ||
d1712369 KG |
162 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
163 | #define SPD_EEPROM_ADDRESS1 0x51 | |
164 | #define SPD_EEPROM_ADDRESS2 0x52 | |
e02aea61 | 165 | #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */ |
28a96671 | 166 | #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ |
d1712369 KG |
167 | |
168 | /* | |
169 | * Local Bus Definitions | |
170 | */ | |
171 | ||
172 | /* Set the local bus clock 1/8 of platform clock */ | |
173 | #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 | |
174 | ||
175 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* Start of PromJet */ | |
176 | #ifdef CONFIG_PHYS_64BIT | |
177 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
178 | #else | |
179 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
180 | #endif | |
181 | ||
182 | #define CONFIG_SYS_BR0_PRELIM \ | |
183 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ | |
184 | BR_PS_16 | BR_V) | |
185 | #define CONFIG_SYS_OR0_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ | |
186 | | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) | |
187 | ||
188 | #define CONFIG_SYS_BR1_PRELIM \ | |
189 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) | |
190 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
191 | ||
192 | #define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ | |
193 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
194 | #ifdef CONFIG_PHYS_64BIT | |
195 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
196 | #else | |
197 | #define PIXIS_BASE_PHYS PIXIS_BASE | |
198 | #endif | |
199 | ||
200 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) | |
201 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ | |
202 | ||
203 | #define PIXIS_LBMAP_SWITCH 7 | |
204 | #define PIXIS_LBMAP_MASK 0xf0 | |
205 | #define PIXIS_LBMAP_SHIFT 4 | |
206 | #define PIXIS_LBMAP_ALTBANK 0x40 | |
207 | ||
208 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
209 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
210 | ||
211 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
212 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
213 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
214 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
215 | ||
14d0a02a | 216 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
d1712369 | 217 | |
2a9fab82 SX |
218 | #if defined(CONFIG_RAMBOOT_PBL) |
219 | #define CONFIG_SYS_RAMBOOT | |
220 | #endif | |
221 | ||
e02aea61 KG |
222 | /* Nand Flash */ |
223 | #if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) | |
224 | #define CONFIG_NAND_FSL_ELBC | |
225 | #ifdef CONFIG_NAND_FSL_ELBC | |
226 | #define CONFIG_SYS_NAND_BASE 0xffa00000 | |
227 | #ifdef CONFIG_PHYS_64BIT | |
228 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
229 | #else | |
230 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
231 | #endif | |
232 | ||
233 | #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} | |
234 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
235 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
236 | #define CONFIG_CMD_NAND | |
237 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
238 | ||
239 | /* NAND flash config */ | |
240 | #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
241 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
242 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
243 | | BR_MS_FCM /* MSEL = FCM */ \ | |
244 | | BR_V) /* valid */ | |
245 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
246 | | OR_FCM_PGS /* Large Page*/ \ | |
247 | | OR_FCM_CSCT \ | |
248 | | OR_FCM_CST \ | |
249 | | OR_FCM_CHT \ | |
250 | | OR_FCM_SCY_1 \ | |
251 | | OR_FCM_TRLX \ | |
252 | | OR_FCM_EHTR) | |
253 | ||
254 | #define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ | |
255 | #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
256 | #endif /* CONFIG_NAND_FSL_ELBC */ | |
257 | #endif | |
258 | ||
d1712369 KG |
259 | #define CONFIG_SYS_FLASH_EMPTY_INFO |
260 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
261 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS} | |
262 | ||
263 | #define CONFIG_BOARD_EARLY_INIT_F | |
264 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
265 | #define CONFIG_MISC_INIT_R | |
266 | ||
267 | #define CONFIG_HWCONFIG | |
268 | ||
269 | /* define to use L1 as initial stack */ | |
270 | #define CONFIG_L1_INIT_RAM | |
271 | #define CONFIG_SYS_INIT_RAM_LOCK | |
272 | #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ | |
273 | #ifdef CONFIG_PHYS_64BIT | |
274 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf | |
275 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR | |
276 | /* The assembler doesn't like typecast */ | |
277 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ | |
278 | ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ | |
279 | CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) | |
280 | #else | |
281 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ | |
282 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 | |
283 | #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS | |
284 | #endif | |
553f0982 | 285 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ |
d1712369 | 286 | |
25ddd1fb | 287 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
d1712369 KG |
288 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
289 | ||
290 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
291 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
292 | ||
293 | /* Serial Port - controlled on board with jumper J8 | |
294 | * open - index 2 | |
295 | * shorted - index 1 | |
296 | */ | |
297 | #define CONFIG_CONS_INDEX 1 | |
298 | #define CONFIG_SYS_NS16550 | |
299 | #define CONFIG_SYS_NS16550_SERIAL | |
300 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
301 | #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) | |
302 | ||
303 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
304 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
305 | ||
306 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500) | |
307 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600) | |
308 | #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) | |
309 | #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) | |
310 | ||
311 | /* Use the HUSH parser */ | |
312 | #define CONFIG_SYS_HUSH_PARSER | |
313 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
314 | ||
315 | /* pass open firmware flat tree */ | |
316 | #define CONFIG_OF_LIBFDT | |
317 | #define CONFIG_OF_BOARD_SETUP | |
318 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
319 | ||
320 | /* new uImage format support */ | |
321 | #define CONFIG_FIT | |
322 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
323 | ||
324 | /* I2C */ | |
325 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
326 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
327 | #define CONFIG_I2C_MULTI_BUS | |
328 | #define CONFIG_I2C_CMD_TREE | |
329 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ | |
330 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
331 | #define CONFIG_SYS_I2C_OFFSET 0x118000 | |
332 | #define CONFIG_SYS_I2C2_OFFSET 0x118100 | |
333 | ||
334 | /* | |
335 | * RapidIO | |
336 | */ | |
a09b9b68 | 337 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 |
d1712369 | 338 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 339 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull |
d1712369 | 340 | #else |
a09b9b68 | 341 | #define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 |
d1712369 | 342 | #endif |
a09b9b68 | 343 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 | 344 | |
a09b9b68 | 345 | #define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000 |
d1712369 | 346 | #ifdef CONFIG_PHYS_64BIT |
a09b9b68 | 347 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull |
d1712369 | 348 | #else |
a09b9b68 | 349 | #define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000 |
d1712369 | 350 | #endif |
a09b9b68 | 351 | #define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */ |
d1712369 KG |
352 | |
353 | /* | |
354 | * General PCI | |
355 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
356 | */ | |
357 | ||
358 | /* controller 1, direct to uli, tgtid 3, Base address 20000 */ | |
359 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
360 | #ifdef CONFIG_PHYS_64BIT | |
361 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 | |
362 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
363 | #else | |
364 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
365 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
366 | #endif | |
367 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
368 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 | |
369 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
370 | #ifdef CONFIG_PHYS_64BIT | |
371 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull | |
372 | #else | |
373 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 | |
374 | #endif | |
375 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
376 | ||
377 | /* controller 2, Slot 2, tgtid 2, Base address 201000 */ | |
378 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
379 | #ifdef CONFIG_PHYS_64BIT | |
380 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 | |
381 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
382 | #else | |
383 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
384 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
385 | #endif | |
386 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
387 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 | |
388 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
389 | #ifdef CONFIG_PHYS_64BIT | |
390 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull | |
391 | #else | |
392 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 | |
393 | #endif | |
394 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
395 | ||
396 | /* controller 3, Slot 1, tgtid 1, Base address 202000 */ | |
02bb4989 | 397 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 |
d1712369 KG |
398 | #ifdef CONFIG_PHYS_64BIT |
399 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
400 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull | |
401 | #else | |
402 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 | |
403 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 | |
404 | #endif | |
405 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ | |
406 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 | |
407 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 | |
408 | #ifdef CONFIG_PHYS_64BIT | |
409 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull | |
410 | #else | |
411 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 | |
412 | #endif | |
413 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
414 | ||
1bf8e9fd KG |
415 | /* controller 4, Base address 203000 */ |
416 | #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 | |
417 | #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull | |
418 | #define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ | |
419 | #define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 | |
420 | #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull | |
421 | #define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ | |
422 | ||
d1712369 | 423 | /* Qman/Bman */ |
24995d82 | 424 | #define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ |
d1712369 KG |
425 | #define CONFIG_SYS_BMAN_NUM_PORTALS 10 |
426 | #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 | |
427 | #ifdef CONFIG_PHYS_64BIT | |
428 | #define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull | |
429 | #else | |
430 | #define CONFIG_SYS_BMAN_MEM_PHYS CONFIG_SYS_BMAN_MEM_BASE | |
431 | #endif | |
432 | #define CONFIG_SYS_BMAN_MEM_SIZE 0x00200000 | |
433 | #define CONFIG_SYS_QMAN_NUM_PORTALS 10 | |
434 | #define CONFIG_SYS_QMAN_MEM_BASE 0xf4200000 | |
435 | #ifdef CONFIG_PHYS_64BIT | |
436 | #define CONFIG_SYS_QMAN_MEM_PHYS 0xff4200000ull | |
437 | #else | |
438 | #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE | |
439 | #endif | |
440 | #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 | |
441 | ||
442 | #define CONFIG_SYS_DPAA_FMAN | |
443 | #define CONFIG_SYS_DPAA_PME | |
444 | /* Default address of microcode for the Linux Fman driver */ | |
445 | #define CONFIG_SYS_FMAN_FW_ADDR 0xEF000000 | |
446 | #ifdef CONFIG_PHYS_64BIT | |
447 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS 0xFEF000000ULL | |
448 | #else | |
449 | #define CONFIG_SYS_FMAN_FW_ADDR_PHYS CONFIG_SYS_FMAN_FW_ADDR | |
450 | #endif | |
451 | ||
452 | #ifdef CONFIG_SYS_DPAA_FMAN | |
453 | #define CONFIG_FMAN_ENET | |
454 | #endif | |
455 | ||
456 | #ifdef CONFIG_PCI | |
d1712369 KG |
457 | #define CONFIG_NET_MULTI |
458 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
459 | #define CONFIG_E1000 | |
460 | ||
d1712369 KG |
461 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
462 | #define CONFIG_DOS_PARTITION | |
463 | #endif /* CONFIG_PCI */ | |
464 | ||
465 | /* SATA */ | |
466 | #ifdef CONFIG_FSL_SATA_V2 | |
467 | #define CONFIG_LIBATA | |
468 | #define CONFIG_FSL_SATA | |
469 | ||
470 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
471 | #define CONFIG_SATA1 | |
472 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
473 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
474 | #define CONFIG_SATA2 | |
475 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
476 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
477 | ||
478 | #define CONFIG_LBA48 | |
479 | #define CONFIG_CMD_SATA | |
480 | #define CONFIG_DOS_PARTITION | |
481 | #define CONFIG_CMD_EXT2 | |
482 | #endif | |
483 | ||
484 | #ifdef CONFIG_FMAN_ENET | |
485 | #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x1c | |
486 | #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x1d | |
487 | #define CONFIG_SYS_FM1_DTSEC3_PHY_ADDR 0x1e | |
488 | #define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x1f | |
489 | #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 4 | |
490 | ||
d1712369 KG |
491 | #define CONFIG_SYS_FM2_DTSEC1_PHY_ADDR 0x1c |
492 | #define CONFIG_SYS_FM2_DTSEC2_PHY_ADDR 0x1d | |
493 | #define CONFIG_SYS_FM2_DTSEC3_PHY_ADDR 0x1e | |
494 | #define CONFIG_SYS_FM2_DTSEC4_PHY_ADDR 0x1f | |
495 | #define CONFIG_SYS_FM2_10GEC1_PHY_ADDR 0 | |
d1712369 KG |
496 | |
497 | #define CONFIG_SYS_TBIPA_VALUE 8 | |
498 | #define CONFIG_MII /* MII PHY management */ | |
499 | #define CONFIG_ETHPRIME "FM1@DTSEC1" | |
500 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
501 | #endif | |
502 | ||
503 | /* | |
504 | * Environment | |
505 | */ | |
d1712369 KG |
506 | #define CONFIG_ENV_SIZE 0x2000 |
507 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
508 | ||
509 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
510 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
511 | ||
512 | /* | |
513 | * Command line configuration. | |
514 | */ | |
515 | #include <config_cmd_default.h> | |
516 | ||
a000b795 | 517 | #define CONFIG_CMD_DHCP |
d1712369 KG |
518 | #define CONFIG_CMD_ELF |
519 | #define CONFIG_CMD_ERRATA | |
a000b795 | 520 | #define CONFIG_CMD_GREPENV |
d1712369 KG |
521 | #define CONFIG_CMD_IRQ |
522 | #define CONFIG_CMD_I2C | |
523 | #define CONFIG_CMD_MII | |
524 | #define CONFIG_CMD_PING | |
525 | #define CONFIG_CMD_SETEXPR | |
526 | ||
527 | #ifdef CONFIG_PCI | |
528 | #define CONFIG_CMD_PCI | |
529 | #define CONFIG_CMD_NET | |
530 | #endif | |
531 | ||
532 | /* | |
533 | * USB | |
534 | */ | |
535 | #define CONFIG_CMD_USB | |
536 | #define CONFIG_USB_STORAGE | |
537 | #define CONFIG_USB_EHCI | |
538 | #define CONFIG_USB_EHCI_FSL | |
539 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
540 | #define CONFIG_CMD_EXT2 | |
541 | ||
542 | #define CONFIG_MMC | |
543 | ||
544 | #ifdef CONFIG_MMC | |
545 | #define CONFIG_FSL_ESDHC | |
546 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
547 | #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT | |
548 | #define CONFIG_CMD_MMC | |
549 | #define CONFIG_GENERIC_MMC | |
550 | #define CONFIG_CMD_EXT2 | |
551 | #define CONFIG_CMD_FAT | |
552 | #define CONFIG_DOS_PARTITION | |
553 | #endif | |
554 | ||
555 | /* | |
556 | * Miscellaneous configurable options | |
557 | */ | |
558 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
559 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
560 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
561 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
562 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
563 | #ifdef CONFIG_CMD_KGDB | |
564 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
565 | #else | |
566 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
567 | #endif | |
568 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
569 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
570 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
571 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
572 | ||
573 | /* | |
574 | * For booting Linux, the board info and command line data | |
575 | * have to be in the first 16 MB of memory, since this is | |
576 | * the maximum mapped by the Linux kernel during initialization. | |
577 | */ | |
578 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ | |
7c57f3e8 | 579 | #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */ |
d1712369 | 580 | |
d1712369 KG |
581 | #ifdef CONFIG_CMD_KGDB |
582 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
583 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
584 | #endif | |
585 | ||
586 | /* | |
587 | * Environment Configuration | |
588 | */ | |
589 | #define CONFIG_ROOTPATH /opt/nfsroot | |
590 | #define CONFIG_BOOTFILE uImage | |
591 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
592 | ||
593 | /* default location for tftp and bootm */ | |
594 | #define CONFIG_LOADADDR 1000000 | |
595 | ||
596 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
597 | ||
598 | #define CONFIG_BAUDRATE 115200 | |
599 | ||
600 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
c2b3b640 EM |
601 | "hwconfig=fsl_ddr:ctlr_intlv=cacheline," \ |
602 | "bank_intlv=cs0_cs1\0" \ | |
d1712369 KG |
603 | "netdev=eth0\0" \ |
604 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
14d0a02a | 605 | "ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0" \ |
c2b3b640 EM |
606 | "tftpflash=tftpboot $loadaddr $uboot && " \ |
607 | "protect off $ubootaddr +$filesize && " \ | |
608 | "erase $ubootaddr +$filesize && " \ | |
609 | "cp.b $loadaddr $ubootaddr $filesize && " \ | |
610 | "protect on $ubootaddr +$filesize && " \ | |
611 | "cmp.b $loadaddr $ubootaddr $filesize\0" \ | |
d1712369 KG |
612 | "consoledev=ttyS0\0" \ |
613 | "ramdiskaddr=2000000\0" \ | |
614 | "ramdiskfile=p4080ds/ramdisk.uboot\0" \ | |
615 | "fdtaddr=c00000\0" \ | |
616 | "fdtfile=p4080ds/p4080ds.dtb\0" \ | |
617 | "bdev=sda3\0" \ | |
618 | "c=ffe\0" \ | |
619 | "fman_ucode="MK_STR(CONFIG_SYS_FMAN_FW_ADDR_PHYS)"\0" | |
620 | ||
621 | #define CONFIG_HDBOOT \ | |
622 | "setenv bootargs root=/dev/$bdev rw " \ | |
623 | "console=$consoledev,$baudrate $othbootargs;" \ | |
624 | "tftp $loadaddr $bootfile;" \ | |
625 | "tftp $fdtaddr $fdtfile;" \ | |
626 | "bootm $loadaddr - $fdtaddr" | |
627 | ||
628 | #define CONFIG_NFSBOOTCOMMAND \ | |
629 | "setenv bootargs root=/dev/nfs rw " \ | |
630 | "nfsroot=$serverip:$rootpath " \ | |
631 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
632 | "console=$consoledev,$baudrate $othbootargs;" \ | |
633 | "tftp $loadaddr $bootfile;" \ | |
634 | "tftp $fdtaddr $fdtfile;" \ | |
635 | "bootm $loadaddr - $fdtaddr" | |
636 | ||
637 | #define CONFIG_RAMBOOTCOMMAND \ | |
638 | "setenv bootargs root=/dev/ram rw " \ | |
639 | "console=$consoledev,$baudrate $othbootargs;" \ | |
640 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
641 | "tftp $loadaddr $bootfile;" \ | |
642 | "tftp $fdtaddr $fdtfile;" \ | |
643 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
644 | ||
645 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
646 | ||
647 | #endif /* __CONFIG_H */ |